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| Number | Title | Issue Date |
| 8120184 | Semiconductor constructions and methods of forming layers The invention includes methods of forming layers conformally over undulating surface topographies associated with semiconductor substrates. The undulating surface topographies can first be exposed to one or more of titanium oxide, neodymium oxide, yttrium oxide, zir... | 02/21/2012 |
| 7939943 | Nitride semiconductor device including an electrode in ohmic contact with a P-type nitride semiconductor contact layer A nitride semiconductor device with a p electrode having no resistance between itself and other electrodes, and a method of manufacturing the same are provided. A p electrode is formed of a first Pd film, a Ta film, and a second Pd film, which is an antioxidant film... | 05/10/2011 |
| 7880305 | Technology for fabrication of packaging interface substrate wafers with fully metallized vias through the substrate wafer The invention is the technology of providing a packaging intermediate product that can serve as an interface substrate that is to be positioned between different circuitry types where the dimensions are approaching the sub 100 micrometer range. The invention involve... | 02/01/2011 |
| 7868456 | Semiconductor device and method for fabricating the same A semiconductor device in which the resistance of a copper wiring to electromigration is increased. The copper wiring is formed so that copper grains will be comparatively large in a central portion of the copper wiring and so that copper grains will be comparativel... | 01/11/2011 |
| 7795738 | Nitride semiconductor device A nitride semiconductor device with a p electrode having no resistance between itself and other electrodes, and a method of manufacturing the same are provided. A p electrode is formed of a first Pd film, a Ta film, and a second Pd film, and on a p-type contact laye... | 09/14/2010 |
| 7737559 | Semiconductor constructions The invention includes methods of forming layers conformally over undulating surface topographies associated with semiconductor substrates. The undulating surface topographies can first be exposed to one or more of titanium oxide, neodymium oxide, yttrium oxide, zir... | 06/15/2010 |
| 7732924 | Semiconductor wiring structures including dielectric cap within metal cap layer Semiconductor wiring structures including a dielectric layer having a metal wiring line therein, a via extending downwardly from the metal wiring line, a metal cap layer over the metal wiring line, and a local dielectric cap positioned within a portion of the metal ... | 06/08/2010 |
| 7723851 | Method of fabricating ultra-deep vias and three-dimensional integrated circuits using ultra-deep vias A method of forming a high aspect ratio via opening through multiple dielectric layers, a high aspect ratio electrically conductive via, methods of forming three-dimension integrated circuits, and three-dimensional integrated circuits. The methods include forming a ... | 05/25/2010 |
| 7545043 | Device comprising multi-layered thin film having excellent adhesive strength and method for fabricating the same A device comprises a multi-layered thin film having excellent adhesion due to the method of fabricating the same. More particularly, the device includes a multi-layered thin film consisting of a tantalum nitride layer, a tantalum layer formed on the tantalum nitride... | 06/09/2009 |
| 7459788 | Ohmic electrode structure of nitride semiconductor device An ohmic electrode structure of a nitride semiconductor device having a nitride semiconductor. The ohmic electrode structure is provided with a first metal film formed on the nitride semiconductor and a second metal film formed on the first metal film. The first met... | 12/02/2008 |
| 7435670 | Bit line barrier metal layer for semiconductor device and process for preparing the same The present invention relates to a bit line barrier metal layer for a semiconductor device and a process for preparing the same, the process comprising: forming bit line contact on an insulation layer vapor-deposited on an upper part of a substrate so as to expose a... | 10/14/2008 |
| 7402883 | Back end of the line structures with liner and noble metal layer A back end of the line (BEOL) structure of a semiconductor device is presented. In one embodiment, the structure may include a first liner layer disposed on an intermediate interconnect structure, the intermediate interconnect structure having an opening disposed be... | 07/22/2008 |
| 7400042 | Substrate with adhesive bonding metallization with diffusion barrier A metallization layer that includes a tantalum layer located on the component, a tantalum silicide layer located on the tantalum layer, and a platinum silicide layer located on the tantalum silicide layer. In another embodiment the invention is a component having a ... | 07/15/2008 |
| 7372163 | Semiconductor device and production method therefor A semiconductor device provided with: a first interconnection layer provided on a semiconductor substrate; an interlevel insulation film provided over the first interconnection layer; a second interconnection layer of gold provided as an uppermost interconnection la... | 05/13/2008 |
| 7319270 | Multi-layer electrode and method of forming the same An interconnect includes an opening formed in a dielectric layer. A conductive barrier is deposited in the opening, over which a first conductive layer is deposited. A conductive oxide is deposited over the first conductive layer, and a second conductive layer, form... | 01/15/2008 |
| RE39932 | Semiconductor interconnect formed over an insulation and having moisture resistant material A plurality of metal wires are formed on an underlying interlayer insulating film. Areas among the metal wires are filled with a buried insulating film of a silicon oxide film with a small dielectric constant (i.e., a first dielectric film), and thus, a parasitic ca... | 12/04/2007 |
| 7300869 | Integrated barrier and seed layer for copper interconnect technology An integrated barrier and seed layer that is useful for creating conductive pathways in semiconductor devices. The barrier portion of the integrated layer prevents diffusion of the conductive material into the underlying dielectric substrate while the seed portion p... | 11/27/2007 |
| 7297630 | Methods of fabricating via hole and trench A method of fabricating a via and a trench is disclosed. A disclosed method comprises: forming a via hole and a trench in a interlayer dielectric layer on a semiconductor substrate where a predetermined device is formed; depositing a thin Hf layer on the substrate; ... | 11/20/2007 |
| 7291505 | Method of manufacturing a ferroelectric device The invention relates to a ferroelectric device (10) with a body (11) comprising a substrate (1) and a ferroelectric layer (2) provided with a connection conductor (3) on a side facing away from the substrate (1), which ferr... | 11/06/2007 |
| 7279732 | Enhanced atomic layer deposition A method of enhanced atomic layer deposition is described. In an embodiment, the enhancement is the use of plasma. Plasma begins prior to flowing a second precursor into the chamber. The second precursor reacts with a prior precursor to deposit a layer on the substr... | 10/09/2007 |
| 7276801 | Designs and methods for conductive bumps Methods, techniques, and structures relating to die packaging. In one exemplary implementation, a die package interconnect structure includes a semiconductor substrate and a first conducting layer in contact with the semiconductor substrate. The first conducting lay... | 10/02/2007 |
| 7262473 | Metal to polysilicon contact in oxygen environment A method for forming a contact capable of tolerating an O2 environment up to several hundred degrees Celsius for several hours is disclosed. To slow down the metal oxide front of the metal layer at the metal-polysilicon interface, the metal layer is surro... | 08/28/2007 |
| 7256500 | Semiconductor device using metal nitride as insulating film A first insulating film is formed on a semiconductor substrate. A second insulating film made of insulating metal nitride is formed on the first insulating film. A recess is formed through the second insulating film and reaches a position deeper than an upper surfac... | 08/14/2007 |
| 7253522 | Integrated capacitor for RF applications with Ta adhesion layer A precision RF passive component including: a silicon substrate; a first dielectric layer deposited above the silicon substrate; a first metal layer formed above the first dielectric layer; a second dielectric layer formed above the first metal layer; and a second m... | 08/07/2007 |
| 7253501 | High performance metallization cap layer A semiconductor device having a nonconductive cap layer comprising a first metal element. The nonconductive cap layer comprises a first metal nitride, a first metal oxide, or a first metal oxynitride over conductive lines and an insulating material between the condu... | 08/07/2007 |
| 7253519 | Chip packaging structure having redistribution layer with recess A chip structure comprising a chip, a redistribution layer, a second passivation layer and at least a bump is provided. The chip has a first passivation layer and at least a bonding pad. The first passivation layer exposes the bonding pad and has at least a recess. ... | 08/07/2007 |
| 7250679 | Semiconductor device and method for fabricating the same The semiconductor device comprises a lower interconnection part 12 which is formed on a silicon substrate 10 and includes an inter-layer insulation film 36 formed of a low-k film 32 and a hydrophilic insulation film 34 formed on th... | 07/31/2007 |
| 7230337 | Semiconductor device including ladder-shaped siloxane hydride and method for manufacturing same The present invention reduces the effective dielectric constant of the interlayer insulating film while inhibiting the decrease of the reliability of the semiconductor device, which otherwise is caused by a moisture absorption. A copper interconnect comprising a Cu ... | 06/12/2007 |
| 7214418 | Structure having holes and method for producing the same A structure having a hole, including a substrate, a first layer including an alumina hole, and a second layer disposed between the substrate and the fist layer, wherein the second layer contains silicon, and has a smaller hole than the alumina hole. ... | 05/08/2007 |
| 7198887 | Organic anti-reflective coating polymer, its preparation method and organic anti-reflective coating composition comprising the same Disclosed are an organic anti-reflective coating polymer having a structure represented by the following formula I, its preparation method and an organic anti-reflective coating composition with respect to an ultra-fine pattern formation process of the photoresist f... | 04/03/2007 |
| 7193327 | Barrier structure for semiconductor devices An opening in a dielectric layer having a unique barrier layer structure is provided. In an embodiment, the opening is a via and a trench. The barrier layer, which may comprise one or more barrier layers, is formed such that the ratio of the thickness of the barrier... | 03/20/2007 |
| 7187085 | Semiconductor device including dual damascene interconnections A method (and structure) of forming an interconnect on a semiconductor substrate, includes forming a relatively narrow first structure in a dielectric formed on a semiconductor substrate, forming a relatively wider second structure in the dielectric formed on the se... | 03/06/2007 |
| 7183601 | Semiconductor device and method for manufacturing thereof Disclosed in a semiconductor device comprising a semiconductor substrate, and a ferroelectric layer provided above the semiconductor substrate and sandwiched between a lower electrode and an upper electrode, the lower electrode comprising a strontium ruthenate film ... | 02/27/2007 |
| 7176117 | Method for mounting passive components on wafer A method for mounting a passive component on a wafer. A passivation layer is disposed on a wafer having at least one first metal pad and at least one second metal pad thereon, which substantially exposes the first and second metal pads. A capping layer is formed on ... | 02/13/2007 |
| 7176571 | Nitride barrier layer to prevent metal (Cu) leakage issue in a dual damascene structure A method for forming a composite barrier layer that also functions as an etch stop in a damascene process is disclosed. A SiC layer is deposited on a substrate in a CVD process chamber followed by deposition of a silicon nitride layer to complete the composite barri... | 02/13/2007 |
| 7172707 | Sputtered spring films with low stress anisotropy Methods are disclosed for fabricating spring structures that minimize helical twisting by reducing or eliminating stress anisotropy in the thin films from which the springs are formed through manipulation of the fabrication process parameters and/or spring material ... | 02/06/2007 |
| 7167342 | Magnetic recording medium, magnetic recording playback device, and information processing device A magnetic recording medium is provided while including a recording layer in which magnetic materials are in the shape of a circular cylinder and uniformity and size reduction are achieved simultaneously. The magnetic recording medium includes a recording layer and ... | 01/23/2007 |
| 7166544 | Method to deposit functionally graded dielectric films via chemical vapor deposition using viscous precursors A method of forming a graded dielectric layer on an underlying layer including flowing a mixture of a silicon-carbon containing gas, an oxygen containing gas and a carrier gas through a showerhead comprising a blocking plate and a faceplate to form an oxide rich por... | 01/23/2007 |
| 7164207 | Wiring structure for semiconductor device A wiring structure for semiconductor device has a wiring layer that includes copper as main component and a crystal grain promotion layer that promotes enlargement in a crystal grain of the wiring layer. ... | 01/16/2007 |
| 7157780 | Semiconductor device and method for producing the same A gate electrode is formed on a substrate via a gate insulating film. The gate insulating film includes a high dielectric constant film containing a metal, oxygen and hydrogen, and a lower barrier film formed below the high dielectric constant film and containing a ... | 01/02/2007 |
