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| Number | Title | Issue Date |
| 8084863 | Circuitized substrate with continuous thermoplastic support film dielectric layers A circuitized substrate including a dielectric layer having a p-aramid paper impregnated with a halogen-free, low moisture absorptivity resin and not including continuous or semi-continuous fiberglass fibers as part thereof, and a first circuitized layer positioned ... | 12/27/2011 |
| 8080878 | Semiconductor device having insulating film with surface modification layer and method for manufacturing the same Provided is a semiconductor device, which includes an interlayer insulating film formed on a semiconductor substrate, a wiring layer filled in a recess formed in the interlayer insulating film, and a cap insulating film. The interlayer insulating film includes a fir... | 12/20/2011 |
| 8008776 | Chip structure and process for forming the same A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-... | 08/30/2011 |
| 7999386 | Semiconductor device including a guard ring surrounding an inductor A semiconductor device contains a semiconductor substrate, an insulating film formed on the semiconductor substrate, an inductor formed over the semiconductor substrate while placing a portion of the insulating film in between, and a guard ring surrounding the induc... | 08/16/2011 |
| 7932603 | Chip structure and process for forming the same A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-... | 04/26/2011 |
| 7915734 | Chip structure and process for forming the same A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-... | 03/29/2011 |
| 7906849 | Chip structure and process for forming the same A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-... | 03/15/2011 |
| 7893538 | Organic silica film and method for forming same, composition for forming insulating film of semiconductor device and method for producing same, wiring structure and semiconductor device An insulating-film-forming composition for a semiconductor device comprising an organic silica sol with a carbon atom content of 11 to 17 atom % and an organic solvent is disclosed. The organic silica sol comprises a hydrolysis-condensation product P1 and a hydrolys... | 02/22/2011 |
| 7893537 | Semiconductor device At least part of an element isolation region, an interlayer insulating film, and a protection insulating film, other than a gate insulating film (silicon oxide film), is formed of carbon fluoride (CFx, 0.3 | 02/22/2011 |
| 7875981 | Insulating film material, multilayer interconnection structure, method for manufacturing same, and method for manufacturing semiconductor device To provide an insulating film material that can be advantageously used for forming an insulating film having a low dielectric constant and excellent resistance to damage, such as etching resistance and resistance to liquid reagents, a multilayer interconnection stru... | 01/25/2011 |
| 7863749 | Electronic structures utilizing etch resistant boron and phosphorus materials and methods to form same A dense boron-based or phosphorus-based dielectric material is provided. Specifically, the present invention provides a dense boron-based dielectric material comprised of boron and at least one of carbon, nitrogen, and hydrogen or a dense phosphorus-based dielectric... | 01/04/2011 |
| 7863750 | Semiconductor device capable of suppressing warping in a wafer state and manufacturing method thereof In this manufacturing method of a semiconductor device, after a sealing film is applied over an entire surface of a semiconductor wafer and hardened, a second groove for forming a side-section protective film is formed in the sealing film and on the top surface side... | 01/04/2011 |
| 7830013 | Material for forming adhesion reinforcing layer, adhesion reinforcing layer, semiconductor device, and manufacturing method thereof The present invention aims at providing: a material for forming an adhesion reinforcing layer which can reinforce the adhesion between a low dielectric constant film, especially a low dielectric constant film containing an inorganic material, and other members; an a... | 11/09/2010 |
| 7791201 | Integration of dissimilar materials for advanced multifunctional devices A device including a layered heterostructure with an oxygen-containing material, with a carbon layer and an amorphous oxygen diffusion barrier protecting the carbon layer from etching by oxygen. One or more of a metal, a carbide or an oxide may be in contact with th... | 09/07/2010 |
| 7763979 | Organic insulating film, manufacturing method thereof, semiconductor device using such organic insulating film and manufacturing method thereof The dielectric constants of SiC and SiCN that are currently the subjects of much investigation are both 4.5 to 5 or so and that of SiOC, 2.8 to 3.0 or so. With further miniaturization of the interconnection size and the spacing of interconnections brought about by t... | 07/27/2010 |
| RE41369 | Semiconductor device and method of manufacturing the same A semiconductor device includes at least one semiconductor structure having a plurality of external connection portions on an upper surface, and an insulating member which is made of a resin containing reinforcing materials and arranged on a side of the semiconducto... | 06/08/2010 |
| 7728436 | Method for selective deposition of a thin self-assembled monolayer A method for selective deposition of self-assembled monolayers to the surface of a substrate for use as a diffusion barrier layer in interconnect structures is provided comprising the steps of depositing a first self-assembled monolayer to said surface, depositing a... | 06/01/2010 |
| 7646098 | Multilayered circuitized substrate with p-aramid dielectric layers and method of making same A multilayered circuitized substrate including a plurality of dielectric layers each comprised of a p-aramid paper impregnated with a halogen-free, low moisture absorptivity resin including an inorganic filler but not including continuous or semi-continuous fibergla... | 01/12/2010 |
| 7633163 | Very low dielectric constant plasma-enhanced CVD films The present invention provides a method for depositing nano-porous low dielectric constant films by reacting an oxidizable silicon containing compound or mixture comprising an oxidizable silicon component and an oxidizable non-silicon component having thermally liab... | 12/15/2009 |
| 7547971 | Semiconductor integrated circuit device Circuit elements and wirings constituting a circuit, and first electrodes electrically connected to such a circuit are provided on one main surface of a semiconductor substrate. An organic insulating film is formed on the circuit except for openings on the surfaces ... | 06/16/2009 |
| 7518245 | Contact structure of a semiconductor device In one embodiment, a semiconductor device comprises a conductive pad formed in a semiconductor substrate. The semiconductor device further includes a conductive pattern overlying a peripheral region of the conductive pad. The conductive pattern has an opening to exp... | 04/14/2009 |
| 7504727 | Semiconductor interconnect structure utilizing a porous dielectric material as an etch stop layer between adjacent non-porous dielectric materials Interconnect structures possessing a non-porous (dense) low-k organosilicate glass (OSG) film utilizing a porous low-k OSG film as an etch stop layer or a porous low-k OSG film using a non-porous OSG film as a hardmask for use in semiconductor devices are provided h... | 03/17/2009 |
| 7485964 | Dielectric material A dielectric material formed by contacting a low dielectric constant polymer with liquid or supercritical carbon dioxide, under thermodynamic conditions which maintain the carbon dioxide in the liquid or supercritical state, wherein a porous product is formed. There... | 02/03/2009 |
| 7470988 | Chip structure and process for forming the same A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-... | 12/30/2008 |
| 7436064 | Laser process for reliable and low-resistance electrical contacts Disclosed is a method for manufacturing an organic optoelectronic device. The method comprises providing a substrate, disposing a first electrode on the substrate, disposing a metal pad on the substrate, electrically separated from the first electrode, disposing a f... | 10/14/2008 |
| 7429793 | Semiconductor device having an electronic circuit disposed therein A semiconductor device and a fabrication method thereof are provided. A semiconductor device which is packaged as it includes a semiconductor in which an electronic circuit is disposed, the semiconductor device including: a substrate; a semiconductor chip which has ... | 09/30/2008 |
| 7425735 | Multi-layer phase-changeable memory devices A phase-changeable memory device includes a phase-changeable material pattern and first and second electrodes electrically connected to the phase-changeable material pattern. The first and second electrodes are configured to provide an electrical signal to the phase... | 09/16/2008 |
| 7425764 | Top layers of metal for high performance IC's A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an ... | 09/16/2008 |
| 7423300 | Single-mask phase change memory element A memory device. An array of memory elements is formed on a semiconductor chip. A parallel array of word lines extends in a first direction, connecting each memory element to a data source, and a parallel array of bit lines extends in a second direction, connecting ... | 09/09/2008 |
| 7423346 | Post passivation interconnection process and structures A system and method for forming post passivation metal structures is described. Metal interconnections and high quality electrical components, such as inductors, transformers, capacitors, or resistors are formed on a layer of passivation, or on a thick layer of poly... | 09/09/2008 |
| 7422975 | Composite inter-level dielectric structure for an integrated circuit A method is provided for making an inter-level dielectric for a microelectronic device formed on a substrate. The method begins by forming first and second spacer layers over a substrate layer. The spacer layers are formed from a sacrificial dielectric material. Nex... | 09/09/2008 |
| 7420279 | Carbon containing silicon oxide film having high ashing tolerance and adhesion An insulating film used for an interlayer insulating film of a semiconductor device and having a low dielectric constant. The insulating film comprises a carbon containing silicon oxide (SiOCH) film which has Si—CH2 bond therein. The proportion of Si—CH2 bond (1... | 09/02/2008 |
| 7420276 | Post passivation structure for semiconductor chip or wafer The present invention adds one or more thick layers of polymer dielectric and one or more layers of thick, wide metal lines on top of a finished semiconductor wafer, post-passivation. The thick, wide metal lines may be used for long signal paths and can also be used... | 09/02/2008 |
| 7417326 | Semiconductor device and manufacturing method of the same A semiconductor device includes a plurality of electrode layers provided at designated positions of a semiconductor substrate, an organic insulation film formed on the semiconductor substrate by selectively exposing designated areas of the electrode layers, and proj... | 08/26/2008 |
| 7413978 | Substrate, electro-optical device, electronic apparatus, method of forming substrate, method of forming electro-optical device, and method of forming electronic apparatus A contact structure, including: a first conductive layer; a insulating layer formed on the first conductive layer; a second conductive layer formed on the insulating layer; and a columnar structure, buried in a direction of film thickness in the insulating layer, el... | 08/19/2008 |
| 7408260 | Microelectronic assemblies having compliant layers A microelectronic assembly includes a microelectronic element such as a semiconductor chip or wafer having a first surface and contacts accessible at the first surface, a compliant layer overlying the first surface of the microelectronic element, and conductive prot... | 08/05/2008 |
| 7402513 | Method for forming interlayer insulation film It is an object of the present invention to provide a method for forming an interlayer insulation film suppressing the occurrence of voids in the interlayer insulation film. A method for forming an interlayer insulation film of the present invention, comprisi... | 07/22/2008 |
| 7402846 | Electrostatic discharge (ESD) protection structure and a circuit using the same An electrostatic discharge (ESD) protection structure is disclosed. The ESD protection structure includes an active device. The active device includes a plurality of drains. Each of the drains has a contact row and at least one body contact row. The at least one bod... | 07/22/2008 |
| 7397135 | Top layers of metal for high performance IC's A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an ... | 07/08/2008 |
| 7394156 | Semiconductor integrated circuit device and method of producing the same A semiconductor integrated circuit device has a plurality of CMOS-type base cells arranged on a semiconductor substrate and m wiring layers, and gate array type logic cells are composed of the base cells and the wiring layers. Wiring within and between the logic cel... | 07/01/2008 |
