Class 257/758 - Multiple metal levels on semiconductor, separated by insulating layer (e.g., multiple level metallization for integrated circuit)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: Subject matter wherein there are plural layers of metal
No. of patents: 3783
Last issue date: 05/29/2012

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Number	Title	Issue Date
8188603	Post passivation interconnection schemes on top of IC chip A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over...	05/29/2012
8188602	Semiconductor device having multilevel copper wiring layers and its manufacture method To provide a semiconductor device having copper wiring layers and organic insulating resin layers with less separation and its manufacture method. A semiconductor device has: a semiconductor substrate formed with a number of semiconductor elements; a first in...	05/29/2012
8169080	Semiconductor device and method of manufacture thereof A seal ring is provided between a region where a circuit is formed on a semiconductor substrate and a dicing region. The seal ring has a portion where sealing layers of which the cross sectional form is in T-shape are layered and a portion where sealing layers of wh...	05/01/2012
RE43320	Semiconductor device and manufacturing method thereof There is disclosed a semiconductor device comprising a first metal wiring buried in a first wiring groove formed, via a first barrier metal, in a first insulating layer formed on a semiconductor substrate, a second insulating layer formed on the first metal wiring, ...	04/24/2012
8164191	Semiconductor device A semiconductor device including a semiconductor element and a functional member fixed thereto with an adhesive film is provided, where the performance or reliability degradation due to moisture entered by way of the adhesive film itself or the interfaces between th...	04/24/2012
8159070	Chip packages Chip assemblies are disclosed that include a semiconductor substrate, multiple devices in and on the semiconductor substrate, a first metallization structure over the semiconductor substrate, and a passivation layer over the first metallization structure. First and ...	04/17/2012
8154128	3D integrated circuit layer interconnect A three-dimensional 3D interconnect structure with a small footprint is described, useful for connection from above to levels of circuit structures in a multi-level device. Also, an efficient and low cost method for manufacturing the 3D interconnect structure is pro...	04/10/2012
8143724	Standard cell and semiconductor device including the same This invention prevents a break in a signal wire disposed between wire ends due to attenuation and improves production yields of devices. In a standard cell, a first signal wire extends in a first direction. Second and third signal wires extend in a second direction...	03/27/2012
8143723	Highly integrated and reliable DRAM and its manufacture A semiconductor device and its manufacture method wherein the semiconductor substrate has first and second insulating films, the first insulating film being an insulating film other than a silicon nitride film formed at least on a side wall of a conductive pattern i...	03/27/2012
8129843	Methods to mitigate plasma damage in organosilicate dielectrics using a protective sidewall spacer Plasma damage in ultra low k dielectric materials during formation of a dual damascene metal interconnect structure is reduced by providing a protective spacer on sidewalls of a line trench. A densified trench bottom region may be additionally formed directly beneat...	03/06/2012
8129842	Enhanced interconnect structure The present invention provides a semiconductor interconnect structure with improved mechanical strength at the capping layer/dielectric layer/diffusion barrier interface. The interconnect structure has Cu diffusion barrier material embedded in the Cu capping materia...	03/06/2012
8120181	Post passivation interconnection process and structures A system and method for forming post passivation metal structures is described. Metal interconnections and high quality electrical components, such as inductors, transformers, capacitors, or resistors are formed on a layer of passivation, or on a thick layer of poly...	02/21/2012
8120183	Method of forming top electrode for capacitor and interconnection in integrated passive device (IPD) A method of manufacturing a semiconductor device includes providing a substrate having a first conductive layer disposed on a top surface of the substrate. A high resistivity layer is formed over the substrate and the first conductive layer. A dielectric layer is de...	02/21/2012
8120182	Integrated circuit comprising conductive lines and contact structures and method of manufacturing an integrated circuit An integrated circuit comprises a first conductive lines and second lines as well as contact structures being in contact with the first and second conductive lines. The first conductive lines are arranged in a first metallization level, and second conductive lines a...	02/21/2012
8115312	Semiconductor device having a through electrode A semiconductor device 1 has a semiconductor chip 10. The semiconductor chip 10 is constituted as having a semiconductor substrate 12 and an interlayer insulating film 14 on the semiconductor substrate 12. The semiconductor ...	02/14/2012
8115313	Method to form an interconnect A plurality of electrodes are electrically coupled to each other by conductive interconnects formed from selectively sintered nanoparticles. ...	02/14/2012
8110924	Semiconductor device and method for manufacturing same In a DC-DC converter, a multilayer wiring layer is provided on a silicon substrate, and a control circuit configured to control an input circuit and an output circuit is formed in the silicon substrate and the multilayer wiring layer. Moreover, a sealing resin layer...	02/07/2012
8106515	Local metallization and use thereof in semiconductor devices An embodiment of the invention provides a method of creating local metallization in a semiconductor structure, and the use of local metallization so created in semiconductor structures. In one respect, the method includes forming an insulating layer on top of a semi...	01/31/2012
8106514	Semiconductor device having an annular guard ring A semiconductor chip 100 includes a logic unit and an analog unit 153. Furthermore, the semiconductor chip 100 includes a silicon substrate 101; a first insulating film 123 to a sixth insulating film 143 formed on the silico...	01/31/2012
8102053	Displacement detection pattern for detecting displacement between wiring and via plug, displacement detection method, and semiconductor device A displacement detection pattern, usable for detection of a relative displacement between a wiring and a via plug, includes a wiring provided between via plugs and a conductor. The conductor is provided in the same layer level as a level at which the wiring is provi...	01/24/2012
8097949	Control of localized air gap formation in an interconnect stack The present invention relates to a method for fabricating an interconnect stack of an integrated-circuit device. Air gaps are fabricated in the interconnect stack on one or more interconnect levels. The method comprises forming local etch vias (216, 218) betw...	01/17/2012
8093723	Method of manufacturing a semiconductor integrated circuit device In a semiconductor integrated circuit device having plural layers of buried wirings, it is intended to prevent the occurrence of a discontinuity caused by stress migration at an interface between a plug connected at a bottom thereof to a buried wiring and the buried...	01/10/2012
8089155	High performance system-on-chip discrete components using post passivation process A system and method for forming post passivation discrete components, is described. High quality discrete components are formed on a layer of passivation, or on a thick layer of polymer over a passivation layer. ...	01/03/2012
8089157	Contact metallurgy structure A contact metallurgy structure comprising a patterned dielectric layer having vias on a substrate; a silicide layer of cobalt and/or nickel located at the bottom of vias; a contact layer comprising Ti located in vias on top of the silicide layer; a diffusion layer l...	01/03/2012
8089156	Electrode structure for semiconductor chip with crack suppressing dummy metal patterns The bump electrode 100 of the present invention has a structure in which dummy metals 111 are provided in the uppermost layer portion of a silicon 101 between a pad-form wiring metal 102 and a wiring metal 103 such that an edge of ...	01/03/2012
8084862	Interconnect structures with patternable low-k dielectrics and method of fabricating same The present invention provides an interconnect structure in which a patternable low-k material is employed as an interconnect dielectric material. Specifically, this invention relates to single-damascene and dual-damascene low-k interconnect structures with at least...	12/27/2011
8080876	Structure and method for creating reliable deep via connections in a silicon carrier A process and structure for enabling the creation of reliable electrical through-via connections in a semiconductor substrate and a process for filling vias. Problems associated with under etch, over etch and flaring of deep Si RIE etched through-vias are mitigated,...	12/20/2011
8080877	Damascene interconnection structure and dual damascene process thereof A dual damascene process is disclosed. A substrate having a base dielectric layer, a lower wiring layer inlaid in the base dielectric layer, and a cap layer capping the lower wiring layer is provided. A dielectric layer is deposited on the cap layer. A silicon oxide...	12/20/2011
8080875	Interconnection substrate and semiconductor device, manufacturing method of interconnection substrate An interconnection substrate including therein one or more resin layers, each of the resin layers including therein a via-hole penetrating from a top surface to a bottom surface of the resin layer. A via-plug of metal particles is formed in the via-hole. Each of the...	12/20/2011
8076779	Reduction of macro level stresses in copper/low-K wafers A pad structure and passivation scheme which reduces or eliminates IMC cracking in post wire bonded dies during Cu/Low-k BEOL processing. A thick 120 nm barrier layer can be provided between a 1.2 μm aluminum layer and copper. Another possibility is to effectively ...	12/13/2011
8072074	Semiconductor device and method of manufacturing same A technique for enhancing the performance of a memory- and logic-equipped semiconductor device is provided. The semiconductor device comprises a semiconductor substrate (1), an insulating layer (19) on the semiconductor substrate (1), a pluralit...	12/06/2011
8072072	Integrated circuit including different types of gate stacks, corresponding intermediate integrated circuit structure and corresponding integrated circuit The present invention provides a manufacturing method for an integrated circuit and a corresponding integrated circuit. The integrated circuit comprises a plurality of first devices, each first device including a charge storage layer and a control electrode comprisi...	12/06/2011
8072073	Semiconductor device and method of manufacturing same A highly reliable semiconductor device in which connection reliability is assured at very small vias comprises: a semiconductor substrate; a first wiring structure placed on the semiconductor substrate and having one or more first wiring layers, one or more insulati...	12/06/2011
8067838	Semiconductor device having pad structure for preventing and buffering stress of silicon nitride film A semiconductor device having a pad structure for preventing a stress of a silicon nitride film. The semiconductor device includes a semiconductor substrate, a lower structure formed on the semiconductor substrate, a first insulation film formed on the lower structu...	11/29/2011
8067837	Metallization structure over passivation layer for IC chip A semiconductor chip suited for being electrically connected to a circuit element includes a line and a bump. The bump is connected to the line and is adapted to be electrically connected to the line. A plane that is horizontal to an active surface of the semiconduc...	11/29/2011
8058729	Titanium nitride films The use of atomic layer deposition (ALD) to form a conductive titanium nitride layer produces a reliable structure for use in a variety of electronic devices. The structure is formed by depositing titanium nitride by atomic layer deposition onto a substrate surface ...	11/15/2011
8058730	Semiconductor device having a multilayered interconnection structure A semiconductor device according to one embodiment includes: a semiconductor substrate provided with a semiconductor element; a first conductive member formed on the semiconductor substrate; a first insulating film formed on the same layer as the first conductive me...	11/15/2011
8053892	Low resistance and reliable copper interconnects by variable doping A method and system is provided for efficiently varying the composition of the metal interconnects for a semiconductor device. A metal interconnect according to the present disclosure has an intermediate layer on a dielectric material, the intermediate layer having ...	11/08/2011
8049335	System and method for plasma induced modification and improvement of critical dimension uniformity Novel interconnect structures possessing a OSG or polymeric-based (90 nm and beyond BEOL technologies) in which advanced plasma processing is utilized to reduce post lithographic CD non-uniformity (“line edge roughness”) in semiconductor devices. The novel inter...	11/01/2011
8044513	Semiconductor device and semiconductor device manufacturing method A semiconductor device includes a plurality of first MOS transistors has a first gate electrode formed on a first gate insulating film provided in a first transistor region on a semiconductor substrate, a plurality of second MOS transistors has a second gate electro...	10/25/2011

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Class 257/758 - Multiple metal levels on semiconductor, separated by insulating layer (e.g., multiple level metallization for integrated circuit)