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| Number | Title | Issue Date |
| 8102052 | Process for the simultaneous deposition of crystalline and amorphous layers with doping One embodiment of the present invention relates to method for the concurrent deposition of multiple different crystalline structures on a semiconductor body utilizing in-situ differential epitaxy. In one embodiment of the present invention a preparation surface is f... | 01/24/2012 |
| 8026606 | Interconnect layers without electromigration A structure and a method for forming the same. The structure includes (a) an interlevel dielectric (ILD) layer; (b) a first electrically conductive line and a second electrically conductive line both residing in the ILD layer; (c) a diffusion barrier region residing... | 09/27/2011 |
| 7859110 | Solder resist material, wiring board using the solder resist material, and semiconductor package The present invention provides a solder resist material, which can suppress the warpage of a semiconductor package upon exposure to heat or impact even when used in a thin wiring board and meets a demand for size reduction in electronic devices and a higher level of... | 12/28/2010 |
| 7701058 | Undoped polysilicon metal silicide wiring Defect density of a polysilicon metal silicide wiring is reduced by employing a block of undoped polysilicon metal silicide in locations in which dopants are not needed in the underlying polysilicon. Furthermore, detection of presence of defects in the polysilicon m... | 04/20/2010 |
| 7423344 | Bi-layer etch stop process for defect reduction and via stress migration improvement A method of forming a film stack in an integrated circuit, said method comprising depositing a layer of silicon carbide adjacent a first layer of dielectric material, depositing a layer of silicon nitride adjacent the layer of silicon carbide, and depositing a secon... | 09/09/2008 |
| 7397124 | Process of metal interconnects A process of metal interconnects and a structure of metal interconnect produced therefrom are provided. An opening is formed in a dielectric layer. A metal layer is formed over the dielectric layer filling the opening. A film layer is formed on the metal layer and t... | 07/08/2008 |
| 7365010 | Semiconductor device having carbon-containing metal silicide layer and method of fabricating the same Methods of fabricating semiconductor devices having a carbon-containing metal silicide layer and semiconductor devices fabricated by the methods are provided. A representative method includes the steps of preparing a semiconductor substrate and forming a gate electr... | 04/29/2008 |
| 7332811 | Integrated circuit interconnect A method for forming an electrical interconnect overlying a buried contact region of a substrate is characterized by a deposition of a first polycrystalline silicon layer and the patterning and etching of same to form a via. The via is formed in the first polycrysta... | 02/19/2008 |
| 7327030 | Apparatus and method incorporating discrete passive components in an electronic package An apparatus and method for incorporating discrete passive components into an integrated circuit package. A metal layer is formed over a surface of a substrate. A layer of photosensitive material is then formed over the metal layer. Using standard photolithographic ... | 02/05/2008 |
| 7294934 | Low-K dielectric structure and method A low-k dielectric sacrificial material is formed within a microelectronic structure covered with a suitable porous or low density permeable material. At an appropriate time, the underlying sacrificial material is decomposed and diffused away through the overlying p... | 11/13/2007 |
| 7294567 | Semiconductor contact device and method The invention provides an advanced metallization technique for fabricating a memory cell array on a substrate. The array is fabricated by forming discrete and self-aligned vias in a first layer disposed over the array to form contacts to each of the source and drain... | 11/13/2007 |
| 7259416 | Semiconductor device having a conductive plug There is provided a semiconductor device that comprises a first impurity diffusion region formed on a silicon substrate (semiconductor substrate), a first interlayer insulating film (first insulating film) formed over the silicon substrate, a first hole formed in th... | 08/21/2007 |
| 7253519 | Chip packaging structure having redistribution layer with recess A chip structure comprising a chip, a redistribution layer, a second passivation layer and at least a bump is provided. The chip has a first passivation layer and at least a bonding pad. The first passivation layer exposes the bonding pad and has at least a recess. ... | 08/07/2007 |
| 7253121 | Method for forming IMD films A method for forming IMD films. A substrate is provided. A plurality of dielectric films are formed on the substrate, wherein each of the dielectric layers are deposited in-situ in one chamber with only one thermal cycle. ... | 08/07/2007 |
| 7250680 | Semiconductor circuitry constructions The invention includes a method of forming semiconductor circuitry wherein a first semiconductor structure comprising a first monocrystalline semiconductor substrate is bonded to a second semiconductor structure comprising a second monocrystalline semiconductor subs... | 07/31/2007 |
| 7245015 | Display apparatus In a display apparatus, a display panel receives a driving signal from a driving chip through a pad and displays an image in response to the driving signal. The driving chip includes a terminal outputting the driving signal. The driving chip is mounted on the displa... | 07/17/2007 |
| 7214979 | Selectively deposited silicon oxide layers on a silicon substrate A process for selectively depositing a silicon oxide layer onto silicon substrates of different conductivity types is disclosed. The silicon oxide layer is formed by the ozone decomposition of TEOS at relatively low temperatures and relatively high pressures. Use of... | 05/08/2007 |
| 7211896 | Semiconductor device and method of manufacturing the same There is provided a method of manufacturing a semiconductor device in which interconnect capacitance is restrained. The semiconductor device 200 comprises a semiconductor substrate; a second interconnect insulating film 216 constituted of a ladder-type... | 05/01/2007 |
| 7199028 | Method for manufacturing semiconductor device Provided is a method for manufacturing a semiconductor device capable of preventing a solution from penetrating a lower layer by forming a poly silicon layer stacked of the films having the different grain boundary structures at border, wherein the solution is used ... | 04/03/2007 |
| 7151314 | Semiconductor device with superimposed poly-silicon plugs A semiconductor device includes a first insulating layer; a first poly-silicon plug formed in the first insulating layer; a second insulating layer, formed on the first insulating layer; and a second poly-silicon plug that is formed in the second insulating layer. A... | 12/19/2006 |
| 7132363 | Stabilizing fluorine etching of low-k materials Damascene processing is implemented with dielectric barrier films (50, 90, 91) for improved step coverage and reduced contact resistance. Embodiments include the use of two different dielectric films (50, 31) to avoid misalignment problems. Embodiments... | 11/07/2006 |
| 7125763 | Silicided buried bitline process for a non-volatile memory cell A process of fabricating a memory cell that includes a substrate that has a first region and a second region with a channel therebetween by forming a gate above the channel of the substrate, forming a bitline and siliciding the bitline. ... | 10/24/2006 |
| 7118954 | High voltage metal-oxide-semiconductor transistor devices and method of making the same A method for fabricating metal-oxide-semiconductor devices is provided. The method includes forming a gate dielectric layer on a substrate; depositing a polysilicon layer on the gate dielectric layer; forming a resist mask on the polysilicon layer; etching the polys... | 10/10/2006 |
| 7119005 | Semiconductor local interconnect and contact An integrated circuit is provided. A gate dielectric and a gate are provided respectively on and over a semiconductor substrate. A junction is formed adjacent the gate dielectric and a shaped spacer is formed around the gate. A spacer is formed under the shaped spac... | 10/10/2006 |
| 7112854 | Thin-film transistor and method of fabricating the same Provided are a thin-film transistor formed by connecting polysilicon layers having different conductivity types with each other which prevents occurrence of inconvenience resulting from diffusion of impurities and a method of fabricating the same. A drain (6)... | 09/26/2006 |
| 7023090 | Bonding pad and via structure design A bonding pad design, comprising: a substrate; a lower series of metal pads upon the substrate; and an intermediate series of metal pads over the lower series of metal pads. The lower series of metal pads and the intermediate series of metal pads being connected by ... | 04/04/2006 |
| 6995411 | Image sensor with vertically integrated thin-film photodiode An image sensor has a vertically integrated thin-film photodiode. In one implementation, the image sensor has a substrate, an interconnection structure adjacent to the substrate, wherein the interconnection structure includes a top metal layer comprising a plurality... | 02/07/2006 |
| 6987322 | Contact etching utilizing multi-layer hard mask A method for forming contact holes using a multi-layer hard mask. A substrate with a device region and an alignment region having an opening therein to serve as an alignment mark is provided. A dielectric layer is formed overlying the substrate and fills the opening... | 01/17/2006 |
| 6940170 | Techniques for triple and quadruple damascene fabrication The present invention provides integrated circuit fabrication methods and devices wherein triple damascene structures are formed in five consecutive dielectric layers (312, 314, 316, 318 and 320), using two etching sequences. A first etching sequence c... | 09/06/2005 |
| 6921708 | Integrated circuits having low resistivity contacts and the formation thereof using an in situ plasma doping and clean Contact areas comprising doped semiconductor material at the bottom of contact holes are cleaned in a hot hydrogen plasma and exposed in situ during and/or separately from the hot hydrogen clean to a plasma containing the same dopant species as in the semiconductor ... | 07/26/2005 |
| 6894364 | Capacitor in an interconnect system and method of manufacturing thereof A fabrication method for an integrated device having a capacitor in an interconnect system is described. At least a first exposed metal line and a second metal line are provided in an insulating layer. A stack layer is deposited and patterned to form a film stack st... | 05/17/2005 |
| 6876045 | Semiconductor device and process for manufacturing the same This specification relates to a process for manufacturing a semiconductor device, comprising the steps of: forming a lower gate electrode film on a semiconductor substrate 10 via a gate insulating film 11; forming an upper gate electrode film on the lo... | 04/05/2005 |
| 6867474 | Monolithic circuit inductance An inductance integrated in a monolithic circuit, including a conductive spiral having an internal end connected to a connection track, the spiral and the connection track belonging to a same metallization level, in which the connection between the internal end of t... | 03/15/2005 |
| 6852566 | Self-aligned rear electrode for diode array element A PIN active pixel sensor array including self aligned encapsulated electrodes and a method for forming the same the method including forming an electrically conductive layer over a substrate; forming a first doped semiconductor layer over the conductive layer; phot... | 02/08/2005 |
| 6833624 | System and method for row decode in a multiport memory The invention provides overlapping row decode in a multiport memory. Overlapping row decode includes predecode wires positioned on a first metallization layer and configured to address wordline drivers of a first port. A second plurality of predecode wires is locate... | 12/21/2004 |
| 6812551 | Defect-free dielectric coatings and preparation thereof using polymeric nitrogenous porogens Defect-free dielectric coatings comprised of porous polymeric matrices are prepared using nitrogen-containing polymers as pore-generating agents. The dielectric coatings are useful in a number of contexts, including the manufacture of electronic devices such as inte... | 11/02/2004 |
| 6800911 | Method of making a polycide interconnection layer having a silicide film formed on a polycrystal silicon for a semiconductor device A semiconductor device has a semiconductor substrate and a conductive layer formed above the semiconductor substrate. The conductive layer has a silicon film, a silicide film formed on the silicon film, and a high melting-point metal film formed on the silicide film... | 10/05/2004 |
| 6783862 | Toughness, adhesion and smooth metal lines of porous low k dielectric interconnect structures A structure useful for electrical interconnection comprises a substrate; a plurality of porous dielectric layers disposed on the substrate; an etch stop layer disposed between a first of the dielectric layers and a second of the dielectric layers; and at least one t... | 08/31/2004 |
| 6747340 | Multi-level shielded multi-conductor interconnect bus for MEMS A multi-level shielded multi-conductor interconnect bus for use in interconnecting MEM devices with control signal sources and a method of fabricating a multi-level shielded multi-conductor interconnect bus are disclosed. In one embodiment, a multi-level shielded in... | 06/08/2004 |
| 6700211 | Method for forming conductors in semiconductor devices A memory device wherein a diode is serially connected to a programmable resistor and is in electrical communication with a buried digit line. An electrically conductive plug is electrically interposed between the digit line and a strapping layer, thereby ... | 03/02/2004 |
