Quotables
"If you build a better mousetrap, you will catch better mice."
George Gobel
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 7511377 | Semiconductor integrated circuit device and process for manufacturing the same A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer consti... | 03/31/2009 |
| 7423344 | Bi-layer etch stop process for defect reduction and via stress migration improvement A method of forming a film stack in an integrated circuit, said method comprising depositing a layer of silicon carbide adjacent a first layer of dielectric material, depositing a layer of silicon nitride adjacent the layer of silicon carbide, and depositing a secon... | 09/09/2008 |
| 7417290 | Air break for improved silicide formation with composite caps Disclosed is a structure and method for tuning silicide stress and, particularly, for developing a tensile silicide region on a gate conductor of an n-FET in order to optimize n-FET performance. More particularly, a first metal layer-protective cap layer-second meta... | 08/26/2008 |
| 7399702 | Methods of forming silicide Methods of fully siliciding semiconductive materials of semiconductor devices are disclosed. A preferred embodiment comprises depositing an alloy comprised of a first metal and a second metal over a semiconductive material. The device is heated, causing atoms of the... | 07/15/2008 |
| 7397123 | Semiconductor integrated circuit device and process for manufacturing the same A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer consti... | 07/08/2008 |
| 7368801 | Semiconductor electrically programmable fuse element with amorphous silicon layer after programming and method of programming the same A fuse link is formed between first and second terminals. The first and second terminals and fuse link have a polysilicon layer and a layer formed on the polysilicon layer and containing a metal element. At least a portion of the fuse link is an amorphous silicon la... | 05/06/2008 |
| 7294893 | Titanium silicide boride gate electrode A method for use in the fabrication of a gate electrode includes providing a gate oxide layer and forming a titanium boride layer on the oxide layer. An insulator cap layer is formed on the titanium boride layer and thereafter, the gate electrode is formed from the ... | 11/13/2007 |
| 7276442 | Method for forming a metallization layer A method for depositing metal on a semiconductor device having a substrate, an exposed first surface, and an exposed second surface is provided. Metal ions are deposited on the exposed first surface and on the exposed second layer by applying a first voltage between... | 10/02/2007 |
| 7257893 | Efficient wafer processing technology Consistent excess conductive material is provided for plated conductors in integrated circuit metallization, regardless of the size and depth of trenches/vias into which the conductive material is deposited. Accordingly, subsequent processing (e.g., material removal... | 08/21/2007 |
| 7256123 | Method of forming an interface for a semiconductor device In a semiconductor device using a polysilicon contact, such as a poly plug between a transistor and a capacitor in a container cell, an interface is provided where the poly plug would otherwise contact the bottom plate of the capacitor. The interface bars silicon fr... | 08/14/2007 |
| 7250680 | Semiconductor circuitry constructions The invention includes a method of forming semiconductor circuitry wherein a first semiconductor structure comprising a first monocrystalline semiconductor substrate is bonded to a second semiconductor structure comprising a second monocrystalline semiconductor subs... | 07/31/2007 |
| 7241698 | Method for sensor edge and mask height control for narrow track width devices A process for defining and controlling the mask height of sensor devices is disclosed. An RIE-resistant, image layer, such as Cu or NiFe, is deposited after the DLC layer. A combination of RIE and ion milling processes or reactive ion beam etching processes are used... | 07/10/2007 |
| 7241697 | Method for sensor edge control and track width definition for narrow track width devices A process for defining and controlling the track width for sensor devices is disclosed. An RIE-resistant, image layer, such as Cu or NiFe, is deposited after the DLC layer. A combination of RIE and ion milling processes or reactive ion beam etching processes are use... | 07/10/2007 |
| 7228614 | Method of manufacturing a gas flow meter A gas flowmeter capable of reducing a secular change comprises a silicon semiconductor substrate formed with a cavity and a heat element formed above the cavity of the semiconductor substrate by way of an insulating film. The heat element is a silicon (Si) semicondu... | 06/12/2007 |
| 7224009 | Method for forming a low leakage contact in a CMOS imager An imaging device formed as a CMOS semiconductor integrated circuit includes a doped polysilicon contact line between the floating diffusion region and the gate of a source follower output transistor. The doped polysilicon contact line in the CMOS imager decreases l... | 05/29/2007 |
| 7220603 | Method for manufacturing display device and manufacturing apparatus It is an object of the present invention to provide a method of manufacturing a display device, which can display images favorably by insulating a short-circuit portion between an anode and a cathode. Further, it is another object of the invention to provide a metho... | 05/22/2007 |
| 7205668 | Multi-layer printed circuit board wiring layout A multi-layer printed circuit board (PCB) includes a first wire layer, a middle layer above the first wire layer, a second wire layer above the middle layer, and a slanting via formed in the middle layer and the second wire layer. The manufacturing method includes t... | 04/17/2007 |
| 7195499 | Method of repairing a light-emitting device and method of manufacturing a light-emitting device A method of repairing a light-emitting device capable of performing high quality image display even if pinholes are formed when forming an organic compound layer is provided. Device contamination can be prevented during repair. By applying a reverse bias voltage to ... | 03/27/2007 |
| 7189317 | Semiconductor manufacturing system for forming metallization layer A method for forming a metallization layer. A first layer is formed outwardly from a semiconductor substrate. Contact vias are formed through the first layer to the semiconductor substrate. A second layer is formed outwardly from the first layer. Portions of the sec... | 03/13/2007 |
| 7176857 | Light emitting device and method of driving the light emitting device A light emitting device that achieves long life, and which is capable of performing high duty drive, by suppressing initial light emitting element deterioration is provided. Reverse bias application to an EL element (109) is performed one row at a time by for... | 02/13/2007 |
| 7173586 | Element substrate and a light emitting device A light emitting device and an element substrate which are capable of suppressing variations in the luminance intensity of a light emitting element among pixels due to characteristic variations of a driving transistor without suppressing off-current of a switching t... | 02/06/2007 |
| 7147530 | Electroluminescence display device and method of manufacturing the same An object of the present invention is to provide an EL display device, which has a high operating performance and reliability. A third passivation film 45 is disposed so as to be in contact with an EL element 203 which comprises a pixel electrode (anod... | 12/12/2006 |
| 7148546 | MOS transistor gates with doped silicide and methods for making the same Semiconductor devices and fabrication methods are presented, in which transistor gate structures are created using doped metal silicide materials. Upper and lower metal silicides are formed above a gate dielectric, wherein the lower metal silicide is doped with n-ty... | 12/12/2006 |
| 7148535 | Zero capacitance bondpad utilizing active negative capacitance The present invention is an apparatus and system for reducing bondpad capacitance of an integrated circuit. Circuitry of the present invention may produce a negative capacitance approximately equal in magnitude to the capacitance associated with the bondpad and ther... | 12/12/2006 |
| 7144793 | Method of producing crystalline semiconductor material and method of fabricating semiconductor device Disclosed are a method of producing a crystalline semiconductor material capable of improving the crystallinity and a method of fabricating a semiconductor device using the crystalline semiconductor material. An amorphous film is uniformly irradiated with a pulse la... | 12/05/2006 |
| 7129177 | Write head fabrication by inverting order of process steps During fabrication of a write head via holes are first opened in a gap layer, followed by formation of seed layers instead of the other way around. Moreover a first seed layer is formed, and without the first seed layer being used a second seed layer is formed. The ... | 10/31/2006 |
| 7126195 | Method for forming a metallization layer A method for forming a metallization layer (30). A first layer (14) is formed outwardly from a semiconductor substrate (10). Contact vias (16) are formed through the first layer (14) to the semiconductor substrate (10). A se... | 10/24/2006 |
| 7112847 | Smooth fin topology in a FinFET device A semiconductor device includes a semiconductor fin formed on an insulator and sidewall spacers formed adjacent the sides of the fin. A gate material layer is formed over the fin and the sidewall spacers and etched to form a gate. The presence of the sidewall spacer... | 09/26/2006 |
| 7112854 | Thin-film transistor and method of fabricating the same Provided are a thin-film transistor formed by connecting polysilicon layers having different conductivity types with each other which prevents occurrence of inconvenience resulting from diffusion of impurities and a method of fabricating the same. A drain (6)... | 09/26/2006 |
| 7091610 | Self-aligned contacts to gates The present invention describes methods, apparatus, and systems related to polysilicon gate contact openings over active regions formed by a separate mask to provide enough control of dielectric removal to produce a contact opening at least down to the gate layer bu... | 08/15/2006 |
| 7064068 | Method to improve planarity of electroplated copper Narrow trenches in a substrate tend to fill more rapidly than wide trenches This results in a non-planar surface once all trenches have been filled. The present invention solves this problem by performing the electro-deposition in two steps. The plating bath used du... | 06/20/2006 |
| 7061110 | Ohmic contact to semiconductor devices and method of manufacturing the same An ohmic contact of semiconductor and its manufacturing method are disclosed. The present invention provides a low resistivity ohmic contact so as to improve the performance and reliability of the semiconductor device. This ohmic contact is formed by first coating a... | 06/13/2006 |
| 7061114 | Structure and method for contact pads having a protected bondable metal plug over copper-metallized integrated circuits An integrated circuit having copper interconnecting metallization (311, 312) protected by a first, inorganic overcoat layer (320), portions of the metallization exposed in windows (301, 302) opened through the thickness of the first overcoat lay... | 06/13/2006 |
| 7061186 | EL display device and electronic apparatus An EL display device capable of clear, multi-gradation color display, and an electronic device having the EL display device, are provided. Gradation display is performed in accordance with a time division driver method which controls by the amount of time an EL elem... | 06/13/2006 |
| 7053454 | Semiconductor component, method for producing the semiconductor component, and method for producing electrical connections between individual circuit elements A fabrication method produces an integrated component on a semiconductor substrate and having a plurality of electrode connections formed to project from to the main surface of the substrate. The electrode connections are simultaneously formed by removing the electr... | 05/30/2006 |
| 7052944 | Thin-film transistor and method of manufacture thereof A thin-film transistor is provided which prevents the degradation of transistor characteristics due to ion channeling. A thin-film transistor (10) includes thin crystalline silicon (2) including source and drain regions (2a) and a channel... | 05/30/2006 |
| 7030451 | Method and apparatus for performing nickel salicidation A method and apparatus for performing nickel salicidation is disclosed. The nickel salicide process typically includes: forming a processed substrate including partially fabricated integrated circuit components and a silicon substrate; incorporating nitrogen into th... | 04/18/2006 |
| 7015080 | Manufacturing method of semiconductor device The present invention makes it is possible to provide a manufacturing method of a semiconductor device by which damage by plasma process or doping process during a LDD formation process can be reduced as much as possible. Charge density to be stored in a gate electr... | 03/21/2006 |
| 7005744 | Conductor line stack having a top portion of a second layer that is smaller than the bottom portion A structure and method are provided for a conductor line stack of an integrated circuit. The conductor line stack includes a layer of a first material such as heavily doped polysilicon or a metal silicide. A layer of a second material such as a metal is formed over ... | 02/28/2006 |
| 6995411 | Image sensor with vertically integrated thin-film photodiode An image sensor has a vertically integrated thin-film photodiode. In one implementation, the image sensor has a substrate, an interconnection structure adjacent to the substrate, wherein the interconnection structure includes a top metal layer comprising a plurality... | 02/07/2006 |
