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| Number | Title | Issue Date |
| 7928571 | Device having dual etch stop liner and reformed silicide layer and related methods The present invention provides a semiconductor device having dual silicon nitride liners and a reformed silicide layer and related methods for the manufacture of such a device. The reformed silicide layer has a thickness and resistance substantially similar to a sil... | 04/19/2011 |
| 7919863 | Semiconductor constructions Some embodiments include methods of forming semiconductor constructions. Oxide is formed over a substrate, and first material is formed over the oxide. Second material is formed over the first material. The second material may be one or both of polycrystalline and a... | 04/05/2011 |
| 7898083 | Method for low stress flip-chip assembly of fine-pitch semiconductor devices A device including a first body (101) with terminals (102) on a surface (101a), each terminal having a metallic connector (110), which is shaped as a column substantially perpendicular to the surface. Preferably, the connectors hav... | 03/01/2011 |
| 7834458 | Interconnect structure for semiconductor devices A cap layer for a copper interconnect structure formed in a first dielectric layer is provided. In an embodiment, the cap layer may be formed by an in-situ deposition process in which a process gas comprising germanium, arsenic, tungsten, or gallium is introduced, t... | 11/16/2010 |
| 7800226 | Integrated circuit with metal silicide regions A method for forming a metal silicide region in a silicon region of a semiconductor substrate. The method comprises forming a metal layer over the silicon region, then in succession forming a titanium and a titanium nitride layer thereover. As the substrate is heate... | 09/21/2010 |
| RE41670 | Sram cell fabrication with interlevel Dielectric planarization A 4-T SRAM cell in which two layers of permanent SOG (with an intermediate oxide layer) are used to provide planarization between the first and topmost poly layers. ... | 09/14/2010 |
| 7781890 | Structure and method for parallel testing of dies on a semiconductor wafer In accordance with an embodiment of the present invention, a semiconductor wafer has a plurality of dies each having a circuit and a plurality of contact pads. The plurality of contact pads include a first contact pad to receive a power supply voltage, a second cont... | 08/24/2010 |
| 7750471 | Metal and alloy silicides on a single silicon wafer Methods and apparatus relating to a single silicon wafer having metal and alloy silicides are described. In one embodiment, two different silicides may be provided on the same wafer. Other embodiments are also disclosed. ... | 07/06/2010 |
| 7741714 | Bond pad structure with stress-buffering layer capping interconnection metal layer A bond pad structure for an integrated circuit chip has a stress-buffering layer between a top interconnection level metal layer and a bond pad layer to prevent damages to the bond pad structure from wafer probing and packaging impacts. The stress-buffering layer is... | 06/22/2010 |
| 7705459 | Semiconductor devices and methods of forming interconnection lines therein An example disclosed semiconductor device includes a semiconductor substrate, a lower interlayer insulating layer formed on the substrate, a lower wire formed on the lower interlayer insulating layer, and an upper interlayer insulating layer which is formed on the l... | 04/27/2010 |
| 7692303 | Semiconductor device and manufacturing method thereof A semiconductor device includes: a P-type semiconductor layer formed in a surface region of a semiconductor substrate; a first gate insulating film formed on the P-type semiconductor layer; a first gate electrode; and a first source region and a first drain region f... | 04/06/2010 |
| 7659627 | Photodiode A photodiode balanced in increased sensitivity and speed. The photodiode includes a semiconductor substrate, an active region formed on the semiconductor substrate, and a comb electrode connected to the active region. The comb electrode includes a plurality of elect... | 02/09/2010 |
| 7608926 | Nonvolatile semiconductor memory device A new method to polish down conductive lines in the manufacture of an integrated circuit device is achieved. The method comprises providing a plurality of conductive lines overlying a substrate. A high density plasma (HDP) oxide layer is deposited overlying the subs... | 10/27/2009 |
| 7566974 | Doped polysilicon via connecting polysilicon layers The invention provides for polysilicon vias connecting conductive polysilicon layers formed at different heights. Polysilicon vias are advantageously used in a monolithic three dimensional memory array of charge storage transistors. Polysilicon vias according to the... | 07/28/2009 |
| 7432559 | Silicide formation on SiGe A semiconductor structure includes a first silicon-containing layer comprising an element selected from the group consisting essentially of carbon and germanium wherein the silicon-containing layer has a first atomic percentage of the element to the element and sili... | 10/07/2008 |
| 7429779 | Semiconductor device having gate electrode connection to wiring layer A semiconductor device includes a semiconductor substrate having an electrode formed above a surface thereof; a first insulating resin layer that is provided over the semiconductor substrate and has a first opening defined at a position corresponding to the electrod... | 09/30/2008 |
| 7423344 | Bi-layer etch stop process for defect reduction and via stress migration improvement A method of forming a film stack in an integrated circuit, said method comprising depositing a layer of silicon carbide adjacent a first layer of dielectric material, depositing a layer of silicon nitride adjacent the layer of silicon carbide, and depositing a secon... | 09/09/2008 |
| 7402863 | Trench FET with reduced mesa width and source contact inside active trench A trench FET has source contacts which contact the entire top surface of source regions, and contact a portion of side walls of the source regions. The side walls of the source regions form a portion of the side walls of the trenches in the trench FET. ... | 07/22/2008 |
| 7372072 | Semiconductor wafer with test structure The invention relates to a semiconductor wafer (1) having a plurality of first sawing regions (201-211) running parallel to one another in a first direction (X) and a plurality of second sawing regions (301-311) running parallel to... | 05/13/2008 |
| 7365430 | Semiconductor device and method of manufacturing the same Disclosed herein is a semiconductor device and method of manufacturing the same. A step between a memory cell formed in a cell region and a transistor formed in a peripheral circuit region is minimized, and the height of a gate in the memory cell is minimized. Accor... | 04/29/2008 |
| 7361597 | Semiconductor device and method of fabricating the same A semiconductor device incorporating an alloy layer formed on a substrate; a gate electrode, a source electrode, and a drain electrode formed on the alloy layer at predetermined intervals therebetween; a gate insulating layer formed on the gate electrode in a gate e... | 04/22/2008 |
| 7358172 | Poly filled substrate contact on SOI structure Embodiments herein present a method for forming a poly filled substrate contact on a SOI structure. The method forms an insulator on a substrate and forms a substrate contact hole within the insulator. The insulator surface level is higher than final structure. Next... | 04/15/2008 |
| 7351651 | Structure and method for contact pads having a recessed bondable metal plug over of copper-metallized integrated circuits A metal structure for an integrated circuit, which has copper interconnecting metallization (311) protected by an overcoat layer (320). A portion of the metallization is exposed in a window (301) opened through the thickness of the overcoat laye... | 04/01/2008 |
| 7342314 | Device having a useful structure and an auxiliary structure The present invention provides a device having a useful structure which is arranged on a substrate and has a useful structure side edge. In addition, an auxiliary structure is arranged on the substrate adjacent to the useful structure, the auxiliary structure having... | 03/11/2008 |
| 7335930 | Borderless contact structures An SRAM cell. The SRAM cell including: a first gate segment common to a first PFET and a first NFET, a second gate segment common to a second PFET and a second NFET; a first silicide layer contacting a first end of the first gate segment and a drain of the second PF... | 02/26/2008 |
| 7327035 | System and method for providing a low frequency filter pole Systems are provided for producing a low frequency filter pole. A first bond pad is coupled to a power source. A second bond pad is inductively connected to the first bond pad by a first bond wire. A capacitor is connected to the second bond pad. A third bond pad is... | 02/05/2008 |
| 7326960 | Semiconductor circuit constructions The invention includes a method of forming semiconductor circuitry wherein a first semiconductor structure comprising a first monocrystalline semiconductor substrate is bonded to a second semiconductor structure comprising a second monocrystalline semiconductor subs... | 02/05/2008 |
| 7315077 | Molded leadless package having a partially exposed lead frame pad Provided are a molded leadless package, and a sawing type molded leadless package and method of manufacturing same. The molded leadless package includes a lead frame pad having first and second surfaces opposite to each other. A semiconductor chip is adhered to the ... | 01/01/2008 |
| 7309921 | Semiconductor device Leakage current generated in a PN junction diode is reduced, and charge-up current caused by plasma treatment in formation of wiring connected to the PN junction diode is controlled. An N+ region as a first conductive type impurity region provided in a Si... | 12/18/2007 |
| 7279918 | Methods for wafer level burn-in A method, circuit and system for determining burn-in reliability from wafer level burn-in are disclosed. The method includes recording the number of failures in each IC die in nonvolatile elements on-chip at points in time over the duration of wafer level burn-in te... | 10/09/2007 |
| 7276433 | Methods of forming integrated circuitry, methods of forming memory circuitry, and methods of forming field effect transistors The invention includes methods of forming integrated circuitry, methods of forming memory circuitry, and methods of forming field effect transistors. In one implementation, conductive metal silicide is formed on some areas of a substrate and not on others. In one im... | 10/02/2007 |
| 7276922 | Closed-grid bus architecture for wafer interconnect structure An interconnect structure employs a closed-grid bus to link an integrated circuit tester channel to an array of input/output (I/O) pads on a semiconductor wafer so that the tester channel can concurrently communicate with all of the I/O pads. The interconnect struct... | 10/02/2007 |
| 7271486 | Retarding agglomeration of Ni monosilicide using Ni alloys A method for providing a low resistance non-agglomerated Ni monosilicide contact that is useful in semiconductor devices. Where the inventive method of fabricating a substantially non-agglomerated Ni alloy monosilicide comprises the steps of: forming a metal alloy l... | 09/18/2007 |
| 7262473 | Metal to polysilicon contact in oxygen environment A method for forming a contact capable of tolerating an O2 environment up to several hundred degrees Celsius for several hours is disclosed. To slow down the metal oxide front of the metal layer at the metal-polysilicon interface, the metal layer is surro... | 08/28/2007 |
| 7259104 | Sample surface processing method A surface processing method of a sample having a mask layer that does not contain carbon as a major component formed on a substance to be processed, the substance being a metal, semiconductor and insulator deposited on a silicon substrate, includes the steps of inst... | 08/21/2007 |
| 7235482 | Method of manufacturing a contact interconnection layer containing a metal and nitrogen by atomic layer deposition for deep sub-micron semiconductor technology An atomic layer deposition method is used to deposit a TiN or TiSiN film having a thickness of about 50 nm or less on a substrat. A titanium precursor which is tetrakis(dimethylamido)titanium (TDMAT), tetrakis(diethylamido)titanium (TDEAT), or Ti{OCH(CH3)... | 06/26/2007 |
| 7232751 | Semiconductor device and manufacturing method therefor According to the manufacturing method of the semiconductor device of the present invention, an oxide film is formed on a metal film formed on a main surface of a semiconductor substrate by exposing the metal film to the oxidizing gas. The oxide film is then reduced ... | 06/19/2007 |
| 7230337 | Semiconductor device including ladder-shaped siloxane hydride and method for manufacturing same The present invention reduces the effective dielectric constant of the interlayer insulating film while inhibiting the decrease of the reliability of the semiconductor device, which otherwise is caused by a moisture absorption. A copper interconnect comprising a Cu ... | 06/12/2007 |
| 7217661 | Small grain size, conformal aluminum interconnects and method for their formation A first layer of titanium nitride (TiN) is formed on a semiconductor structure, such as an interconnect via. Then, a second layer of TiN is formed on the first layer of TiN. The first layer of TiN is amorphous. The second layer of TiN is polycrystalline, having a mi... | 05/15/2007 |
| 7214613 | Cross diffusion barrier layer in polysilicon A semiconductor device includes a cross diffusion barrier layer sandwiched between a gate layer and an electrode layer. The gate layer has a first gate portion of doped polysilicon of first conductivity type adjacent to a second gate portion doped polysilicon of sec... | 05/08/2007 |
