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| Number | Title | Issue Date |
| 8188601 | Semiconductor subassemblies with interconnects and methods for manufacturing the same A semiconductor subassembly is provided for use in a switching module of an inverter circuit for a high power, alternating current motor application. The semiconductor subassembly includes a wafer having first and second opposed metallized faces; a semiconductor swi... | 05/29/2012 |
| 8188600 | Semiconductor device and method of fabricating the same The present invention provides a semiconductor device which is capable of enhancing adhesion at an interface between a wire-protection film and copper, suppressing dispersion of copper at the interface to avoid electromigration and stress-inducing voids, and having ... | 05/29/2012 |
| 8022543 | Underbump metallurgy for enhanced electromigration resistance A first metallic diffusion barrier layer is formed on a last level metal plate exposed in an opening of a passivation layer. Optionally, a metallic adhesion promotion layer is formed on the first metallic diffusion barrier layer. An elemental metal conductive layer ... | 09/20/2011 |
| 7816789 | Germanium-containing dielectric barrier for low-k process A semiconductor structure and methods of forming the same are provided. The semiconductor structure includes a semiconductor substrate; a first dielectric layer over the semiconductor substrate; a conductive wiring in the first dielectric layer; and a copper germani... | 10/19/2010 |
| 7791200 | Approach to high temperature wafer processing At temperatures near, and above, 385° C., gold can diffuse into silicon and into some contact materials. Gold, however, is an excellent material because it is corrosion resistant, electrically conductive, and highly reliable. Using an adhesion layer and removing go... | 09/07/2010 |
| 7737556 | Encapsulated damascene with improved overlayer adhesion An integrated circuit device comprising a partially embedded and encapsulated damascene structure and method for forming the same to improve adhesion to an overlying dielectric layer, the integrated circuit device including a conductive material partially embedded i... | 06/15/2010 |
| 7635919 | Low modulus stress buffer coating in microelectronic devices A method for protecting an electronic component including a semiconductor chip with a first elastic modulus includes steps as follows. At least one application of a first protective substance is applied on an outer surface of the semiconductor chip. The first protec... | 12/22/2009 |
| 7605469 | Atomic layer deposited tantalum containing adhesion layer Apparatus and methods of fabricating an atomic layer deposited tantalum containing adhesion layer within at least one dielectric material in the formation of a metal, wherein the atomic layer deposition tantalum containing adhesion layer is sufficiently thin to mini... | 10/20/2009 |
| 7545042 | Structure combining an IC integrated substrate and a carrier, and method of manufacturing such structure The present invention provides a structure combining an IC integrated substrate and a carrier, which comprises a carrier and an IC integrated substrate formed on the carrier. The interface between the IC integrated substrate and the carrier has a specific area at wh... | 06/09/2009 |
| 7528488 | Method for connecting electrodes, surface-treated wiring board and adhesive film used in the method, and electrode-connected structure The present invention relates to a method for connecting electrodes comprising: interposing the polyphthalide represented by the formula (I): wherein R represents a divalent aromatic hydrocarbon gro... | 05/05/2009 |
| 7470986 | Mounting structure, electro-optical device, and electronic apparatus A mounting structure is provided. The mounting structure includes: a substrate; a line formed on the substrate; an electronic component in which a terminal having a protrusion protruded to the substrate and made of an elastic material and a conductive member dispose... | 12/30/2008 |
| 7470987 | Semiconductor device and its manufacture method capable of preventing short circuit of electrodes when semiconductor device is mounted on sub-mount substrate A confronting surface of a substrate faces a first surface of a semiconductor element. Extension layers are formed on the substrate at positions facing electrodes on the semiconductor element. A levee film is disposed on one of the confronting surface and the first ... | 12/30/2008 |
| 7422977 | Copper adhesion improvement device and method A semiconductor device, in which a semiconductor integrated circuit having a multi-level interconnection structure is formed, according to an embodiment of the present invention, comprises a copper wiring and an insulating layer formed on a top surface of the copper... | 09/09/2008 |
| 7420278 | Semiconductor device The present invention provides a semiconductor device capable of preventing occurrence of cracking and the like, taking a large area, where wiring and the like that function as elemental devices can be arranged, within a plurality of interlayer insulation films, and... | 09/02/2008 |
| 7417264 | Top-emitting nitride-based light emitting device and method of manufacturing the same Provided are a top-emitting N-based light emitting device and a method of manufacturing the same. The device includes a substrate, an n-type clad layer, an active layer, a p-type clad layer, and a multi ohmic contact layer, which are sequentially stacked. The multi ... | 08/26/2008 |
| 7417316 | Wired circuit forming board, wired circuit board, and thin metal layer forming method A wired circuit forming board that can provide improved adhesion between an insulating layer and a conductive pattern and can also prevent delamination in a thin metal layer, a wired circuit board for which the same wired circuit forming board is used, and a thin me... | 08/26/2008 |
| 7405481 | Glue layer for adhesion improvement between conductive line and etch stop layer in an integrated circuit chip In an integrated circuit chip, a conductive line is formed in a first IMD layer. The conductive line is formed of a conductive line material that tends to form an oxide when exposed to an oxygen-containing substance. A glue layer is formed on the conductive line. Th... | 07/29/2008 |
| 7405484 | Semiconductor device containing stacked semiconductor chips and manufacturing method thereof An adhesive film is formed on an electrode film, and a coating film is formed thereon. Nickel, chrome, molybdenum, tungsten, aluminum or an alloy of them is used as a constituent material of the adhesive film. Gold, silver, platinum or an alloy of them is used as a ... | 07/29/2008 |
| 7402909 | Microelectronic package interconnect and method of fabrication thereof A method of interconnecting and an interconnect is provided to connect a first component and a second component of an integrated circuit. The interconnect includes a plurality of Carbon Nanotubes (CNTs), which provide a conducting path between the first component an... | 07/22/2008 |
| 7375005 | Method for reclaiming and reusing wafers Embodiments of the present invention provide a method for reclaiming and reusing a wafer. In one embodiment, a method for reclaiming a wafer comprises providing a used, nonproductive wafer having a semiconductor substrate and a polysilicon layer formed on the semico... | 05/20/2008 |
| 7361976 | Data carrier with a module with a reinforcement strip In a lead-frame configuration (60), a module (70) and a data carrier (72), two connecting plates (12, 13) of the module (70), which are each intended for connection to a connecting contact or bump (47, 48) of a chip (41 | 04/22/2008 |
| 7362491 | Heated glass panels and methods for making electrical contact with electro-conductive films A heated glass panel assembly according to one embodiment of the invention may include a substrate having an electro-conductive film provided thereon. A conductor is positioned in contact with the electro-conductive film. A resilient material is positioned in contac... | 04/22/2008 |
| 7355281 | Method for making semiconductor device having a high-k gate dielectric layer and a metal gate electrode A method for making a semiconductor device is described. That method comprises forming a first dielectric layer on a substrate, then forming a trench within the first dielectric layer. After forming a second dielectric layer on the substrate, a first metal layer is ... | 04/08/2008 |
| 7348671 | Vias having varying diameters and fills for use with a semiconductor device and methods of forming semiconductor device structures including same A method for forming electrical interconnects having different diameters and filler materials through a semiconductor wafer comprises forming first and second openings through a semiconductor, wherein the first opening has a narrower width (smaller diameter) than th... | 03/25/2008 |
| 7335925 | Semiconductor device A semiconductor device for adequately removing heat generated by a semiconductor element is provided. A semiconductor device 100 is equipped with a substrate 2, having a bottom surface 2b and an element mounting surface 2a w... | 02/26/2008 |
| 7335587 | Post polish anneal of atomic layer deposition barrier layers A method for forming a semiconductor device is disclosed wherein atomic layer deposition (ALD) precursor species and/or by-product absorbed by an ILD are outgassed and/or neutralized prior to subsequently patterning the semiconductor device, thereby improving the ab... | 02/26/2008 |
| 7335989 | Semiconductor device and production method therefor A semiconductor device provided with: a first interconnection layer provided on a semiconductor substrate; an interlevel insulation film provided over the first interconnection layer; a barrier layer provided between the first interconnection layer and the interleve... | 02/26/2008 |
| 7329956 | Dual damascene cleaning method A semiconductor structure having a pore sealed portion of a dielectric layer is provided. Exposed pores of the dielectric material are sealed using an anisotropic plasma so that pores along the bottom of the opening are sealed, and pores along sidewalls of the openi... | 02/12/2008 |
| 7327033 | Copper alloy via bottom liner Improved mechanical and adhesive strength and resistance to breakage of copper integrated circuit interconnections is obtained by forming a copper alloy in a copper via/wiring connection in an integrated circuit while minimizing adverse electrical effects of the all... | 02/05/2008 |
| 7315082 | Semiconductor device having integrated circuit contact A process for forming vertical contacts in the manufacture of integrated circuits, and devices so manufactured, is disclosed. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch ... | 01/01/2008 |
| 7304383 | TFT substrate for liquid crystal display apparatus and method of manufacturing the same There are provided a TFT substrate for an LCD apparatus and a method of manufacturing the same. A substrate (10), a diffusion barrier layer (11) and a copper alloy layer (12) are formed on the TFT substrate, consecutively. The copper alloy inclu... | 12/04/2007 |
| 7301241 | Semiconductor device for preventing defective filling of interconnection and cracking of insulating film The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 | 11/27/2007 |
| 7294931 | Method and apparatus for selective deposition A method for selectively depositing a source material on a wafer is disclosed. In one embodiment, a wafer is having at least one recessed feature is provided. A top surface of the wafer is then coated with an inhibiting material. Finally, a source material is select... | 11/13/2007 |
| 7288489 | Process for thinning a semiconductor workpiece The present invention provides an apparatus and method for use in processing semiconductor workpieces. The new apparatus and method allows for the production of thinner workpieces that at the same time remain strong. Particularly, a chuck is provided that includes a... | 10/30/2007 |
| 7285858 | Semiconductor device and its manufacture method capable of preventing short circuit of electrodes when semiconductor device is mounted on sub-mount substrate A confronting surface of a substrate faces a first surface of a semiconductor element. Extension layers are formed on the substrate at positions facing electrodes on the semiconductor element. A levee film is disposed on one of the confronting surface and the first ... | 10/23/2007 |
| 7276801 | Designs and methods for conductive bumps Methods, techniques, and structures relating to die packaging. In one exemplary implementation, a die package interconnect structure includes a semiconductor substrate and a first conducting layer in contact with the semiconductor substrate. The first conducting lay... | 10/02/2007 |
| 7276441 | Dielectric barrier layer for increasing electromigration lifetimes in copper interconnect structures Embodiments of the invention include a copper interconnect structure having increased electromigration lifetime. Such structures can include a semiconductor substrate having a copper layer formed thereon. A dielectric barrier stack is formed on the copper layer. The... | 10/02/2007 |
| 7265432 | Solid state imaging device and method of fabricating the same A method for fabricating a solid state imaging device comprising photoelectric conversion sections and charge transfer sections having single-layered charge transfer electrodes for transferring charges generated in the photoelectric conversion sections, the method i... | 09/04/2007 |
| 7256496 | Semiconductor device having adhesion increasing film to prevent peeling A semiconductor device includes at least one semiconductor constructing body provided on one side of a base member, and having a semiconductor substrate and a plurality of external connecting electrodes provided on the semiconductor substrate. An insulating layer is... | 08/14/2007 |
| 7256503 | Chip underfill in flip-chip technologies A semiconductor structure and method for forming the same. The semiconductor structure includes (a) a substrate and (b) a chip which includes N chip solder balls, N is a positive integer, and the N chip solder balls are in electrical contact with the substrate. The ... | 08/14/2007 |
