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| Number | Title | Issue Date |
| 8106513 | Copper damascene and dual damascene interconnect wiring A copper corrosion resistant integrated circuit. The integrated circuit including: a substrate; a copper diffusion barrier layer on the substrate; a dielectric layer on a top surface of the copper diffusion barrier layer; a copper damascene or dual damascene wire in... | 01/31/2012 |
| 8004082 | Electronic component formed with barrier-seed layer on base material It is an object of the present invention to provide a technology for forming an ULSI fine copper wiring by a simpler method. An electronic component in which a thin alloy film of tungsten and a noble metal used as a barrier-seed layer for an ULSI fine copper wiring ... | 08/23/2011 |
| 7671472 | Semiconductor device and fabrication method for the same A semiconductor device includes a first interlayer insulating film formed on a semiconductor substrate; a second interlayer insulating film formed on the first interlayer film and including a plurality of grooves; a first barrier metal formed on inner surfaces of th... | 03/02/2010 |
| 7554199 | Substrate for evaluation The CMP technology is provided for a damascene wiring structure having a plural-layer wiring that is excellent in flatness and resolvability of Cu residue. An evaluation substrate is provided for evaluating the condition of a CMP that is employed for configuring a s... | 06/30/2009 |
| 7485962 | Semiconductor device, wiring substrate forming method, and substrate processing apparatus A substrate support (201) having a flat supporting surface (201a) is prepared, and a semiconductor substrate (1) is fixed to the substrate supporting surface (201) by attaching a wiring forming surface (1a) to the sup... | 02/03/2009 |
| 7439182 | Semiconductor device and method of fabricating the same A semiconductor and a method of fabricating the same are provided. The method includes: forming an insulation layer on a substrate; forming a trench by selectively etching the insulation layer; electroplating a copper layer in the trench and on the insulation layer ... | 10/21/2008 |
| 7439623 | Semiconductor device having via connecting between interconnects A first insulating film is provided between a lower interconnect and an upper interconnect. The lower interconnect and the upper interconnect are connected to each other by way of a via formed in the first insulating film. A dummy via or an insulating slit is formed... | 10/21/2008 |
| 7414275 | Multi-level interconnections for an integrated circuit chip Multilevel metallization layouts for an integrated circuit chip including transistors having first, second and third elements to which metallization layouts connect. The layouts minimize current limiting mechanism including electromigration by positioning the connec... | 08/19/2008 |
| 7414314 | Semiconductor device and manufacturing method thereof A semiconductor device has a semiconductor substrate, a first insulating film formed on a surface of the semiconductor substrate, a first recess formed in the first insulating film, a first barrier film formed on an inner surface of the first insulating film except ... | 08/19/2008 |
| 7397122 | Metal wiring for semiconductor device and method for forming the same A metal wiring for a semiconductor device and a method for forming the same are provided. The metal wiring includes a first insulating layer and a second insulating layer; an interlayer insulating film formed between the first and second insulating layers, wherein t... | 07/08/2008 |
| 7371679 | Semiconductor device with a metal line and method of forming the same A method of forming a metal line in a semiconductor device including forming an inter-metal dielectric (IMD) layer on the semiconductor substrate including the predetermined pattern, planarizing the IMD layer through a first CMP process, and patterning a via hole on... | 05/13/2008 |
| 7361589 | Copper interconnect systems which use conductive, metal-based cap layers An integrated circuit (IC) may include a substrate, a first dielectric layer adjacent the substrate, and at least one trench in the first dielectric layer. The IC may also include a metal liner within the at least one trench, and a first conductive region including ... | 04/22/2008 |
| 7355247 | Silicon on diamond-like carbon devices Embodiments of the invention provide substrate with an insulator layer on the substrate. The insulator layer may include diamond-like carbon. A device, such a tri-gate transistor may be formed on the diamond-like carbon layer. ... | 04/08/2008 |
| 7351655 | Copper interconnect systems which use conductive, metal-based cap layers An integrated circuit (IC) may include a substrate, a first dielectric layer adjacent the substrate, and at least one trench in the first dielectric layer. The IC may also include a metal liner within the at least one trench, and a first conductive region including ... | 04/01/2008 |
| 7352019 | Capacitance reduction by tunnel formation for use with a semiconductor device A method used during the manufacture of a semiconductor device comprises providing at least first, second, and third spaced conductive structures, where the second conductive structure is interposed between the first and third conductive structures. A first dielectr... | 04/01/2008 |
| 7348676 | Semiconductor device having a metal wiring structure After an insulation layer is formed on a substrate, a contact hole is formed through the insulation layer. A recessed plug is formed to partially fill up the contact hole. The recessed plug has a height substantially smaller than a depth of the contact hole. A metal... | 03/25/2008 |
| 7338907 | Selective etching processes of silicon nitride and indium oxide thin films for FeRAM device applications A dry etch process is described for selectively etching silicon nitride from conductive oxide material for use in a semiconductor fabrication process. Adding an oxidant in the etch gas mixture could increase the etch rate for the silicon nitride while reducing the e... | 03/04/2008 |
| 7339272 | Semiconductor device with scattering bars adjacent conductive lines A semiconductor device and method of manufacture thereof wherein scattering bars are disposed on both sides of an isolated conductive line of a semiconductor device to improve the lithography results. The scattering bars have a sufficient width and are spaced a suff... | 03/04/2008 |
| 7332813 | Semiconductor device A semiconductor device with a metallic region can have a resistance to stress migration and increased reliability. A lower layer wiring made from a barrier metal film (102) and a copper containing metallic film (103) can be formed within an insulating ... | 02/19/2008 |
| 7329952 | Method of fabricating a semiconductor device The semiconductor device comprises a copper interconnection 26b buried in an insulating film 16, and a dummy pattern for chemical mechanical polishing buried in the insulating film 16 near the copper interconnection 26b. The... | 02/12/2008 |
| 7327034 | Compositions for planarization of metal-containing surfaces using halogens and halide salts A planarization method includes providing a metal-containing surface (preferably, a Group VIII metal-containing surface, and more preferably a platinum-containing surface) and positioning it for contact with a polishing surface in the presence of a planarization com... | 02/05/2008 |
| 7323758 | Solid state imaging device and method for producing the same On a light shielding film 7, an anti-oxidation layer 9 covering at least the light shielding film 7 is formed. The anti-oxidation layer 9 is formed under a condition which does not oxidize a surface of the light shielding film 7. T... | 01/29/2008 |
| 7315082 | Semiconductor device having integrated circuit contact A process for forming vertical contacts in the manufacture of integrated circuits, and devices so manufactured, is disclosed. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch ... | 01/01/2008 |
| 7301190 | Structures and methods to enhance copper metallization Disclosed structures and methods inhibit atomic migration and related capacitive-resistive effects between a metallization layer and an insulator layer in a semiconductor structure. One exemplary structure includes an inhibiting layer between an insulator and a meta... | 11/27/2007 |
| 7301107 | Semiconductor device having reduced intra-level and inter-level capacitance An interconnect structure of a semiconductor device designed for reduced intralevel and interlevel capacitance, and includes a lower metal layer and an upper metal layer and an insulating layer interposed between metal layers. Each of the lower metal layer and upper... | 11/27/2007 |
| 7294909 | Electronic package repair process A multilayer ceramic repair process which provides a new electrical repair path to connect top surface vias. The repair path is established between a defective net and a redundant repair net contained within the multilayer ceramic substrate. The defective net and th... | 11/13/2007 |
| 7294570 | Contact integration method A method of making a contact plug and a metallization line structure is disclosed in which a substrate is provided with at least one contact hole within an insulation layer situated on a semiconductor substrate of a semiconductor wafer. A first metal layer is deposi... | 11/13/2007 |
| 7291558 | Copper interconnect wiring and method of forming thereof Capping layer or layers on a surface of a copper interconnect wiring layer for use in interconnect structures for integrated circuits and methods of forming improved integration interconnection structures for integrated circuits by the application of gas-cluster ion... | 11/06/2007 |
| 7291525 | System and method for manufacturing thin film resistors using a trench and chemical mechanical polishing A system and method is disclosed for manufacturing thin film resistors using a trench and chemical mechanical polishing. A trench is etched in a layer of dielectric material and a thin film resistor layer is deposited so that the thin film resistor layer lines the t... | 11/06/2007 |
| 7291920 | Semiconductor structures In one aspect, the invention includes a method of forming a roughened layer of platinum, comprising: a) providing a substrate within a reaction chamber; b) flowing an oxidizing gas into the reaction chamber; c) flowing a platinum precursor into the reaction chamber ... | 11/06/2007 |
| 7286764 | Reconfigurable modulator-based optical add-and-drop multiplexer An optical add and drop multiplexer system comprising a first module for providing a first signal; a second module for providing a second signal; and a modulator for receiving a channel of the first signal at a first location, the first location configured to actuat... | 10/23/2007 |
| 7286354 | Electronic part-mounted substrate, thermal conductive member for electronic part-mounted substrate and liquid-jetting head An electronic part-mounted substrate includes a plate made of metal, an insulating material layer which is formed of a ceramic material on a surface of the plate and which has a surface provided with a heat generating IC thereon, and a thermal conductive member whic... | 10/23/2007 |
| 7285196 | Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals In recent years, copper wiring has emerged as a promising substitute for the aluminum wiring in integrated circuits, because copper offers lower electrical resistance and better reliability at smaller dimensions than aluminum. However, use of copper typically requir... | 10/23/2007 |
| 7283381 | System and methods for addressing a matrix incorporating virtual columns and addressing layers A system and methods for addressing unique locations in a matrix. According to some embodiments, the system includes a plurality of uniquely addressable locations. A plurality of virtual columns that include a plurality of serially connected switch elements provide ... | 10/16/2007 |
| 7282383 | Micromachine production method In a production method of a micromachine having a space between first and second electrodes, a first electrode is formed on a substrate, and then a stopper film is formed on its surface. Next, a second insulating film is formed as to cover the stopper film. The thic... | 10/16/2007 |
| 7271487 | Semiconductor device and method of manufacturing the same The present invention is to improve yield and reliability in a wiring step of a semiconductor device. When an Al wiring on an upper layer is connected through an connection pillar onto an Al wiring on a lower layer embedded in a groove formed on an interlayer insula... | 09/18/2007 |
| 7262505 | Selective electroless-plated copper metallization Structures and methods are provided which include a selective electroless copper metallization. The present invention includes a novel methodology for forming copper vias on a substrate, including depositing a thin film seed layer of Palladium (Pd) or Copper (Cu) on... | 08/28/2007 |
| 7262130 | Methods for making integrated-circuit wiring from copper, silver, gold, and other metals Integrated circuits, the key components in thousands of electronic and computer products, include interconnected networks of electrical components. The components are typically wired, or interconnected, together with aluminum wires. In recent years, researchers have... | 08/28/2007 |
| 7259432 | Semiconductor device for reducing parasitic capacitance produced in the vicinity of a transistor located within the semiconductor device A semiconductor device includes: a gate electrode formed on a substrate; impurity regions formed in the substrate and to both sides of the gate electrode; a first interlayer insulating film formed to cover the gate electrode; and a second interlayer insulating film ... | 08/21/2007 |
| 7253521 | Methods for making integrated-circuit wiring from copper, silver, gold, and other metals Integrated circuits include networks of electrical components that are typically wired, or interconnected, together with aluminum wires. In recent years, researchers have begun using copper in combination with diffusion barriers, rather than aluminum, to form the wi... | 08/07/2007 |
