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| Number | Title | Issue Date |
| 8138603 | Redundancy design with electro-migration immunity An IC interconnect for high direct current (DC) that is substantially immune to electro-migration (EM) damage, a design structure of the IC interconnect and a method of manufacture of the IC interconnect is provided. The structure has electro-migration immunity and ... | 03/20/2012 |
| 8120178 | Tuning fork vibration device and method for manufacturing the same A tuning fork vibration device includes: a SOI substrate having a substrate, an oxide layer formed above the substrate and a semiconductor layer formed above the oxide layer; a tuning fork type vibration section that is formed by processing the semiconductor layer a... | 02/21/2012 |
| 8115311 | Wiring structure in a semiconductor device A wiring structure includes a first insulation layer located on a substrate, and first and second plugs located on the substrate and extending through the first insulation layer. The first plug includes an upper peripheral portion that defines a recess and the secon... | 02/14/2012 |
| 8106511 | Reduced-stress through-chip feature and method of making the same A feature is inscribed in a major surface of a microelectronic workpiece having a material property expressed as a reference coefficient value. The feature includes a first material having a first coefficient value for the material property and a second material hav... | 01/31/2012 |
| 8089153 | Method for eliminating loading effect using a via plug Method for eliminating loading effect using a via plug. According to an embodiment, the present invention provides a method of processing an integrated circuit wherein a loading effect is reduced. The method includes a step for providing a substrate, which is charac... | 01/03/2012 |
| 8076778 | Method for preventing Al-Cu bottom damage using TiN liner A semiconductor device and related method for fabricating the same include providing a stacked structure including an insulating base layer and lower and upper barrier layers with a conductive layer in between, etching the stacked structure to provide a plurality of... | 12/13/2011 |
| 8026604 | Semiconductor devices having contact holes including protrusions exposing contact pads Semiconductor devices are provided including a semiconductor substrate and a first interlayer insulating layer on the semiconductor substrate. A contact pad is provided in the first interlayer insulating layer and a second insulating layer is provided on the first i... | 09/27/2011 |
| 8022542 | Semiconductor device having improved metal wiring A semiconductor device includes a semiconductor substrate, an interlayer insulating film, a tungsten film, a first barrier metal film, a second barrier metal film and a metal wiring film. The interlayer insulating film is formed on the semiconductor substrate, and h... | 09/20/2011 |
| 8008773 | Semiconductor device and method for fabricating semiconductor device According to an aspect of the present invention, there is provided a semiconductor device, including a semiconductor chip including a first electrode and a second electrode of a semiconductor element, the first electrode and the second electrode being configured on ... | 08/30/2011 |
| 7999382 | Semiconductor device and fabrication method for the same A semiconductor device includes a first interlayer insulating film formed on a semiconductor substrate; a second interlayer insulating film formed on the first interlayer film and including a plurality of grooves; a first barrier metal formed on inner surfaces of th... | 08/16/2011 |
| 7956462 | Semiconductor device and manufacturing method thereof A semiconductor device having a multilayer wiring structure and a manufacturing method thereof are provided. A semiconductor device and a manufacturing method thereof are provided in which the reliability and the manufacturing yield are high and the design constrain... | 06/07/2011 |
| 7936066 | Flexible film and display device comprising the same A flexible film is provided. The flexible film includes a dielectric film; and a metal layer disposed on the dielectric film, wherein the ratio of the thickness of the metal layer to the thickness of the dielectric film is about 1:3 to 1:10. Therefore, it is possibl... | 05/03/2011 |
| 7936065 | Semiconductor devices and method of manufacturing them A semiconductor device is provided with a silicon substrate, with a surface for soldering the silicon substrate to a ceramic substrate, and an electrode making contact with the surface of the silicon substrate. The electrode comprises a first conductor layer, a seco... | 05/03/2011 |
| 7928568 | Nanowire-based device having isolated electrode pair A nanowire-based device includes the pair of isolated electrodes and a nanowire bridging between respective surfaces of the isolated electrodes of the pair. Specifically, the nanowire-based device having isolated electrodes comprises: a substrate electrode having a ... | 04/19/2011 |
| 7928567 | Power supply network A power supply network (2) for an integrated circuit is provided, the power supply network (2) comprising a supply grid (4); a plurality of supply pads (6), each supply pad (6) being in electrical contact with an edge of the supply... | 04/19/2011 |
| 7919861 | Semiconductor device and manufacturing method thereof The invention provides a technology for manufacturing a higher performance and higher reliability semiconductor device at low cost and with high yield. The semiconductor device of the invention has a first conductive layer over a first insulating layer; a second ins... | 04/05/2011 |
| 7911058 | Semiconductor chip having island dispersion structure and method for manufacturing the same The present invention has an object to provide a semiconductor chip of high reliability with less risk of breakage. Specifically, the present invention provides a semiconductor chip having a semiconductor silicon substrate including a semiconductor device layer and ... | 03/22/2011 |
| 7884474 | Method for fabricating semiconductor device and semiconductor device A method of fabricating a semiconductor device having an air-gapped multilayer interconnect wiring structure is disclosed. After having formed a first thin film on or above a substrate, define a first opening in the first thin film. Then, deposit a conductive materi... | 02/08/2011 |
| 7868455 | Solving via-misalignment issues in interconnect structures having air-gaps An integrated circuit structure is provided. The integrated circuit structure includes a semiconductor substrate; and a metallization layer over the semiconductor substrate. The metallization layer includes a conductive line; a low-k dielectric region adjacent and h... | 01/11/2011 |
| 7855455 | Lock and key through-via method for wafer level 3 D integration and structures produced A three dimensional device stack structure comprises two or more active device and interconnect layers further connected together using through substrate vias. Methods of forming the three dimensional device stack structure comprise alignment, bonding by lamination,... | 12/21/2010 |
| 7855454 | Semiconductor device structures including nickel plated aluminum, copper, and tungsten structures A method of activating a metal structure on an intermediate semiconductor device structure toward metal plating. The method comprises providing an intermediate semiconductor device structure comprising at least one first metal structure and at least one second metal... | 12/21/2010 |
| 7851913 | Semiconductor device including a power device with first metal layer and second metal layer laterally spaced apart A semiconductor device exhibits a first metal layer, made of a first metal, with at least one contiguous subsection. At least one second metal layer, made of a second metal, is placed on the contiguous subsection of the first metal layer. The second metal is harder ... | 12/14/2010 |
| 7851914 | Semiconductor integrated circuit device A semiconductor integrated circuit device includes a plurality of contact layers located between two lines running in parallel in a first direction. Each of the contact layers has a structure in which an upper contact and a lower contact are coupled together. The pl... | 12/14/2010 |
| 7843062 | Thermally programmable anti-reverse engineering interconnects wherein interconnects only conduct when heated above room temperature An interconnect and method of making the interconnect. The method includes forming a dielectric layer on a substrate, the dielectric layer having a top surface and a bottom surface; forming a first wire and a second wire in the dielectric layer, the first wire separ... | 11/30/2010 |
| 7825514 | Substrate for semiconductor device, resin-sealed semiconductor device, method for manufacturing said substrate for semiconductor device and method for manufacturing said resin-sealed semiconductor device A substrate for a semiconductor device includes: a base plate, a plurality of external terminal portions respectively arranged in a plane on the base plate and having external terminal faces respectively facing the base plate; a plurality of internal terminal portio... | 11/02/2010 |
| 7812451 | Semiconductor device and method of manufacturing the same A semiconductor device includes a first wiring layer, a second wiring layer and a third wiring layer. The first wiring layer is formed on a semiconductor substrate. The second and the third wiring layer wiring layers are arranged in a direction intersecting with the... | 10/12/2010 |
| 7808105 | Semiconductor package and fabricating method thereof A semiconductor package includes a first semiconductor die; a first redistribution layer coupled to a bonding pad of the first semiconductor die; a first solder bump coupled to the first redistribution layer; a second semiconductor die; a second redistribution layer... | 10/05/2010 |
| 7795731 | Semiconductor devices including a topmost metal layer with at least one opening and their methods of fabrication In one embodiment, a semiconductor device has a topmost or highest conductive layer with at least one opening. The semiconductor device includes a semiconductor substrate having a cell array region and an interlayer insulating layer covering the substrate having the... | 09/14/2010 |
| 7795732 | Ceramic wiring board and process for producing the same, and semiconductor device using the same A ceramic wiring board 10 includes a ceramic substrate 11 and a wiring layer 12 formed on the ceramic substrate 11. The wiring layer 12 includes a wiring part 13 and a connection part 14, the wiring part 13 hav... | 09/14/2010 |
| 7750470 | Methods for planarization of dielectric layer around metal patterns for optical efficiency enhancement A method and system for improving planarization and uniformity of dielectric layers for providing improved optical efficiency in CCD and CMOS image sensor devices. In various embodiments, a dielectric planarization method for achieving better optical efficiency incl... | 07/06/2010 |
| 7745933 | Circuit structure and process thereof A circuit structure has a first dielectric layer, a first circuit pattern embedded in the first dielectric layer and having a first via pad, a first conductive via passing through the first dielectric layer and connecting to the first via pad, and an independent via... | 06/29/2010 |
| 7737554 | Pitch by splitting bottom metallization layer An integrated circuit structure includes a semiconductor substrate; a first bottom metallization (M1) layer over the semiconductor substrate; a second M1 layer over the first M1 layer, wherein metal lines in the first and the second M1 la... | 06/15/2010 |
| 7728431 | Electronic component, semiconductor device employing same, and method for manufacturing electronic component Herein disclosed an electronic component having a passivation layer in which an opening that exposes a part of a pad electrode is formed, an underlying metal layer formed on the pad electrode and the passivation layer, and a barrier metal layer formed on the underly... | 06/01/2010 |
| 7714439 | Nitride semiconductor device and method of manufacturing the same A nitride semiconductor device according to the present invention includes a P-type contact layer and a P-type electrode provided on the P-type contact layer. The P-type electrode includes a AuGa film provided on the P-type contact layer, a Au film provided on the A... | 05/11/2010 |
| 7701057 | Semiconductor device having structures for reducing substrate noise coupled from through die vias A semiconductor device having structures for reducing substrate noise coupled from through die vias (TDVs) is described. In one example, a semiconductor device has a substrate, at least one signal through die via (TDV), and ground TDVs. The substrate includes conduc... | 04/20/2010 |
| 7692300 | Printed circuit board and circuit structure for power supply In a printed circuit board, a semiconductor including plural power supply terminals and a semiconductor chip is mounted onto a mounting surface of a printed wiring board, and a bypass capacitor for reducting a power ground noise is provided. Another bypass capacitor... | 04/06/2010 |
| 7687908 | Thin film electrode for high-quality GaN optical devices A thin film electrode for ohmic contact of a p-type GaN semiconductor includes first and second electrode layers sequentially stacked on a p-type GaN layer. The first electrode layer may include an Ni-based alloy, a Cu-based alloy, a Co-based alloy, or a solid solut... | 03/30/2010 |
| 7675173 | Manufacturing semiconductor circuit, corresponding semiconductor circuit, and associated design process A process of manufacturing a semiconductor circuit includes providing a substrate layer, forming a metal layer above the substrate layer, incorporating circuit components in the substrate layer, and electrically connecting the circuit components to the metal layer. ... | 03/09/2010 |
| 7671471 | Method for making a semiconductor device having a high-k dielectric layer and a metal gate electrode A method for making a semiconductor device is described. That method comprises forming a first dielectric layer on a substrate, then forming a trench within the first dielectric layer. After forming a second dielectric layer on the substrate, a first metal layer is ... | 03/02/2010 |
| 7663238 | Wiring material and a semiconductor device having a wiring using the material, and the manufacturing method thereof An object of the present invention is to realize a semiconductor device having a high TFT characteristic. In manufacturing an active matrix display device, electric resistivity of the electrode material is kept low by preventing penetration of oxygen ion into the el... | 02/16/2010 |
