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| Number | Title | Issue Date |
| 7432559 | Silicide formation on SiGe A semiconductor structure includes a first silicon-containing layer comprising an element selected from the group consisting essentially of carbon and germanium wherein the silicon-containing layer has a first atomic percentage of the element to the element and sili... | 10/07/2008 |
| 7368822 | Copper metalized ohmic contact electrode of compound device The present invention provides an ohmic contact for a copper metallization whose heat diffusion is improved and cost is reduced. Therein, the ohmic contact is formed through a depositing and an annealing of three metal layers of Pd, Ge and Cu; and, the contact resis... | 05/06/2008 |
| 7348680 | Electronic device and use thereof The electronic device (100) comprises a semiconductor element (1) (e.g. a transistor), an encapsulation (5) and an electrically conductive layer (3) with a first and a second contact pad (11,12), used as signal pads, and a third co... | 03/25/2008 |
| 7327143 | Miniaturized detection coil former for NMR spectroscopy One exemplary miniaturized detection coil former for NMR spectroscopy includes a macroporous carrier material having a first surface and a second surface situated opposite thereto, as well as a multiplicity of discrete pores formed in the carrier material and having... | 02/05/2008 |
| 7276794 | Junction-isolated vias A process for forming a junction-isolated, electrically conductive via in a silicon substrate and a conductive apparatus to carry electrical signal from one side of a silicon wafer to the other side are provided. The conductive via is junction-isolated from the bulk... | 10/02/2007 |
| 7268413 | Bipolar transistors with low-resistance emitter contacts Many integrated circuits include a type of transistor known as a bipolar junction transistor, which has an emitter contact formed of polysilicon. Unfortunately, polysilicon has a relatively high electrical resistance that poses an obstacle to improving switching spe... | 09/11/2007 |
| 7262505 | Selective electroless-plated copper metallization Structures and methods are provided which include a selective electroless copper metallization. The present invention includes a novel methodology for forming copper vias on a substrate, including depositing a thin film seed layer of Palladium (Pd) or Copper (Cu) on... | 08/28/2007 |
| 7253521 | Methods for making integrated-circuit wiring from copper, silver, gold, and other metals Integrated circuits include networks of electrical components that are typically wired, or interconnected, together with aluminum wires. In recent years, researchers have begun using copper in combination with diffusion barriers, rather than aluminum, to form the wi... | 08/07/2007 |
| 7247524 | Manufacturing method of wiring substrate After a first adhesive layer having high adhesion to a supporting base is locally formed, a second adhesive layer having low adhesion to the supporting base is formed all over the supporting base so as to cover the first adhesive layer. When a wiring structure is se... | 07/24/2007 |
| 7235469 | Semiconductor device and method for manufacturing the same A semiconductor device suitable for the miniaturization and comprising properly controlled Si/SiGe gate electrode comprises an insulator formed on a semiconductor substrate, a first gate electrode formed on the insulator and including silicon-germanium, wherein a ge... | 06/26/2007 |
| 7190043 | Techniques to create low K ILD for beol One aspect of the present subject matter relates to a method for forming an interlayer dielectric (ILD). In various embodiments of the method, an insulator layer is formed, at least one trench is formed in the insulator layer, and a metal layer is formed in the at l... | 03/13/2007 |
| 7186664 | Methods and structures for metal interconnections in integrated circuits A typical integrated-circuit fabrication requires interconnecting millions of microscopic transistors and resistors with metal wires. Making the metal wires flush, or coplanar, with underlying insulation requires digging trenches in the insulation, and then filling ... | 03/06/2007 |
| 7186643 | Barrier-metal-free copper damascene technology using atomic hydrogen enhanced reflow A method for forming conductive contacts and interconnects in a semiconductor structure, and the resulting conductive components are provided. In particular, the method is used to fabricate single or dual damascene copper contacts and interconnects in integrated cir... | 03/06/2007 |
| 7183193 | Integrated device technology using a buried power buss for major device and circuit advantages A method for providing an improved integrated circuit device is disclosed. The method comprises the steps of providing active and passive areas in the substrate, providing a plurality of slots in the substrate after providing the active and passive areas, and oxidiz... | 02/27/2007 |
| 7157387 | Techniques to create low K ILD for BEOL One aspect of the present subject matter relates to a method for forming an interlayer dielectric (ILD). In various embodiments of the method, an insulator layer is formed, at least one trench is formed in the insulator layer, and a metal layer is formed in the at l... | 01/02/2007 |
| 7138718 | Multilevel interconnect structure with low-k dielectric A multilevel interconnect structure with a low-k dielectric constant is fabricated in an integrated circuit structure by the steps of depositing a layer of photoresist on a substrate assembly, etching the photoresist to form openings, forming a metal layer on the ph... | 11/21/2006 |
| 7135774 | Heat resistant ohmic electrode and method of manufacturing the same An aspect of the present invention provides an ohmic electrode that includes an SiC (silicon carbide) substrate, an impurity region selectively formed in a surface of the SiC substrate, an insulating film formed on the surface of the SiC substrate, a contact hole op... | 11/14/2006 |
| 7101778 | Transmission lines for CMOS integrated circuits Improved methods and structures are provided for impedance-controlled low-loss lines in CMOS integrated circuits. The present invention offers a reduction in signal delay. Moreover, the present invention further provides a reduction in skew and crosstalk. Embodiment... | 09/05/2006 |
| 7094682 | Coating of copper and silver air bridge structures to improve electromigration resistance and other applications An improved electrical interconnect for an integrated circuit and methods for providing the same are disclosed. The electrical interconnect includes an air bridge extending through a gaseous medium so as to reduce the capacitance of the interconnect. The air bridge ... | 08/22/2006 |
| 7012312 | Semiconductor device with multilayer conductive structure formed on a semiconductor substrate A highly reliable semiconductor device having a multilayer structure including an insulating film, an adjacent conductive film, and a main conductive film in which adhesive fractures, voids and disconnections are unlikely to occur. Regarding main constituent element... | 03/14/2006 |
| 6969911 | Wiring structure of semiconductor device and production method of the device In a wiring structure of a semiconductor device, dielectric tolerance of the wiring is improved by preventing diffusion of the wiring material. The wiring structure of the semiconductor device includes a first insulating film having plural grooves, plural wiring fil... | 11/29/2005 |
| 6903001 | Techniques to create low K ILD for BEOL One aspect of the present subject matter relates to a method for forming an interlayer dielectric (ILD). In various embodiments of the method, an insulator layer is formed, at least one trench is formed in the insulator layer, and a metal layer is formed in the at l... | 06/07/2005 |
| 6902258 | LDMOS and CMOS integrated circuit and method of making An integrated circuit (IC) is formed on a substrate. The IC has a first well having a first dopant concentration that includes a second conductivity low-voltage transistor. The IC also has a second well having a dopant concentration equal to the first dopant concent... | 06/07/2005 |
| 6879017 | Methods and structures for metal interconnections in integrated circuits A typical integrated-circuit fabrication requires interconnecting millions of microscopic transistors and resistors with metal wires. Making the metal wires flush, or coplanar, with underlying insulation requires digging trenches in the insulation, and then filling ... | 04/12/2005 |
| 6806572 | Structure for contact formation using a silicon-germanium alloy A new method and structure for an improved contact using doped silicon is provided. The structures are integrated into several higher level embodiments. The improved contact has low contact resistivity. Improved junctions are thus provided between an IGFET device an... | 10/19/2004 |
| 6784550 | Thermal processing of metal alloys for an improved CMP process in integrated circuit fabrication A thermal processing method is described which improves integrated circuit metal polishing and increases conductivity following polish. A method of fabricating a metal layer in an integrated circuit is described which comprises the steps of depositing a layer of met... | 08/31/2004 |
| 6767842 | Implementation of Si-Ge HBT with CMOS process A semiconductor device wherein Si—Ge is the base of a bipolar transistor and a Silicon layer is the emitter. A method of making such a semiconductor device including steps of forming a Silicon dioxide layer on a Silicon substrate, using a photo resist application ... | 07/27/2004 |
| 6734515 | Semiconductor light receiving element A semiconductor light receiving element having a light receiving layer (1) formed from a GaN group semiconductor, and an electrode (2) formed on one surface of the light receiving layer as a light receiving surface (1a) in such a way that... | 05/11/2004 |
| 6657303 | Integrated circuit with low solubility metal-conductor interconnect cap An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer ha... | 12/02/2003 |
| 6541859 | Methods and structures for silver interconnections in integrated circuits A typical integrated-circuit fabrication requires interconnecting millions of microscopic transistors and resistors with aluminum wires. Making the aluminum wires flush, or coplanar, with underlying insulation requires digging trenches in the insulation, ... | 04/01/2003 |
| 6525425 | Copper interconnects with improved electromigration resistance and low resistivity Copper interconnects are formed by depositing substantially pure copper into the lower portion of an interconnect opening. The upper portion of the interconnect opening is then filled with doped copper followed by a planarization process. The resulting co... | 02/25/2003 |
| 6514395 | Nanostructure-based high energy capacity material A nanostructure based material is capable of accepting-and reacting with an alkali metal such as lithium. The material exhibits a reversible capacity ranging from at least approximately 900 mAh/g-1,500 mAh/g. The high capacity of the material makes it att... | 02/04/2003 |
| 6452228 | Silicon carbide semiconductor device A vertical type power MOSFET made of silicon carbide includes a surface channel layer doped with nitrogen as dopant with a concentration equal to or less than 1×1015 cm-3. Accordingly, when a gate oxide film is formed on the surface... | 09/17/2002 |
| 6400008 | Surface mount ic using silicon vias in an area array format or same size as die array A die incorporating vertical conductors, or vias, extending from active and passive devices on the active die side to the back side thereof. The vias are preferably formed in the die material matrix by introduction of a conductive material as known in the... | 06/04/2002 |
| 6334939 | Nanostructure-based high energy capacity material A nanostructure based material is capable of accepting and reacting with an alkali metal such as lithium. The material exhibits a reversible capacity ranging from at least approximately 900 mAh/g-1,500 mAh/g. The high capacity of the material makes it att... | 01/01/2002 |
| 6326664 | Transistor with ultra shallow tip and method of fabrication A novel transistor with a low resistance ultra shallow tip region and its method of fabrication. The novel transistor of the present invention has a source/drain extension or tip comprising an ultra shallow region which extends beneath the gate electrode ... | 12/04/2001 |
| 6143655 | Methods and structures for silver interconnections in integrated circuits A typical integrated-circuit fabrication requires interconnecting millions of microscopic transistors and resistors with aluminum wires. Making the aluminum wires flush, or coplanar, with underlying insulation requires digging trenches in the insulation, ... | 11/07/2000 |
| 6100176 | Methods and structures for gold interconnections in integrated circuits A typical integrated-circuit fabrication requires interconnecting millions of microscopic transistors and resistors with aluminum wires. Making the aluminum wires flush, or coplanar, with underlying insulation requires digging trenches in the insulation, ... | 08/08/2000 |
| 6066876 | Integrated circuit arrangement having at least one MOS transistor manufactured by use of a planar transistor layout An integrated circuit arrangement contains an MOS transistor surrounded by an insulation structure, the source and drain thereof being arranged laterally and in different depths. A channel thereof proceeds essentially perpendicular to the surface of the c... | 05/23/2000 |
| 6030894 | Method for manufacturing a semiconductor device having contact plug made of Si/SiGe/Si On a main surface of a silicon substrate of one conductivity type, a diffusion layer of the opposite conductivity type is formed, and the main surface of the silicon substrate is covered by an insulator film. The insulator film is formed with a contact ho... | 02/29/2000 |