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Mountable Printable Placard With Headband
A resilient headband in a shape for being mounted on the head of the user. The headband is equipped with a longitudinal slotted member for holding a placard.
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| Number | Title | Issue Date |
| 7372101 | Sub-lithographics opening for back contact or back gate A low resistance buried back contact for SOI devices. A trench is etched in an insulating layer at minimum lithographic dimension, and sidewalls are deposited in the trench to decrease its width to sublithographic dimension. Conducting material is deposited in the t... | 05/13/2008 |
| 7276796 | Formation of oxidation-resistant seed layer for interconnect applications An interconnect structure of the single or dual damascene type and a method of forming the same, which substantially reduces the surface oxidation problem of plating a conductive material onto a noble metal seed layer are provided. In accordance with the present inv... | 10/02/2007 |
| 7276795 | Small grain size, conformal aluminum interconnects and method for their formation A first layer of titanium nitride (TiN) is formed on a semiconductor structure, such as an interconnect via. Then, a second layer of TiN is formed on the first layer of TiN. The first layer of TiN is amorphous. The second layer of TiN is polycrystalline, having a mi... | 10/02/2007 |
| 7253109 | Method of depositing a tantalum nitride/tantalum diffusion barrier layer system We have discovered a method of providing a thin, approximately from about 2 Å to about 100 Å thick TaN seed layer, which can be used to induce the formation of alpha tantalum when tantalum is deposited over the TaN seed layer. Further, the ... | 08/07/2007 |
| 7235844 | Power composite integrated semiconductor device and manufacturing method thereof A high-reliability power composite integrated semiconductor device uses thick copper electrodes as current collecting electrodes of a power device portion to resist wire resistance needed for reducing ON-resistance. Furthermore, wire bonding connection of the copper... | 06/26/2007 |
| 7187079 | Stacked memory cell having diffusion barriers A nonconductive hydrogen barrier layer is deposited on a substrate and completely covers the surface area over a memory capacitor and a MOSFET switch of an integrated circuit memory cell. A portion of an insulator layer adjacent to the bottom electrode of a memory c... | 03/06/2007 |
| 7105992 | Field emission device having insulated column lines and method of manufacture An FED and a method of manufacture are provided. The FED includes a cathode assembly containing an improved column line structure. The column line structure includes a conductive structure formed on a substrate. A resistive layer is formed on the conductive structur... | 09/12/2006 |
| 7074714 | Method of depositing a metal seed layer on semiconductor substrates We disclose a method of applying a sculptured layer of material on a semiconductor feature surface using ion deposition sputtering, wherein a surface onto which the sculptured layer is applied is protected to resist erosion and contamination by impacting ions of a d... | 07/11/2006 |
| 7052350 | Field emission device having insulated column lines and method manufacture An FED and a method of manufacture are provided. The FED includes a cathode assembly containing an improved column line structure. The column line structure includes a conductive structure formed on a substrate. A resistive layer is formed on the conductive structur... | 05/30/2006 |
| 7042035 | Memory array with high temperature wiring A memory array with components that can withstand high temperature fabrication is provided. Some memory materials require high temperature process steps in order to achieve desired properties. During fabrication, a memory material is deposited on structures that may... | 05/09/2006 |
| 6956293 | Semiconductor device There is provided a semiconductor device having a wafer-level package structure in which CSP structures are formed at a wafer level, which comprises a semiconductor substrate, an electrode pad formed over the semiconductor substrate, and a tail terminal formed to ha... | 10/18/2005 |
| 6955983 | Methods of forming metal interconnections of semiconductor devices by treating a barrier metal layer A metal interconnection of a semiconductor device is fabricated by forming a dielectric pattern including a hole therein on a substrate, and forming a barrier metal layer in the hole and on the dielectric layer pattern outside the hole. At least some of the barrier ... | 10/18/2005 |
| 6936906 | Integration of barrier layer and seed layer The present invention generally relates to filling of a feature by depositing a barrier layer, depositing a seed layer over the barrier layer, and depositing a conductive layer over the seed layer. In one embodiment, the seed layer comprises a copper alloy seed laye... | 08/30/2005 |
| 6919275 | Method of preventing diffusion of copper through a tantalum-comprising barrier layer We disclose a method of applying a sculptured layer of material on a semiconductor feature surface using ion deposition sputtering, wherein a surface onto which the sculptured layer is applied is protected to resist erosion and contamination by impacting ions of a d... | 07/19/2005 |
| 6888245 | Semiconductor device A semiconductor device includes a conductive layer formed on a silicon semiconductor substrate, cobalt silicide films formed in a surface layer of the conductive layer, an interlayer insulating film which covers the silicon semiconductor substrate thereabove, and a ... | 05/03/2005 |
| 6866943 | Bond pad structure comprising tungsten or tungsten compound layer on top of metallization level A bond pad structure formed over a predetermined area of an IC substrate comprising quickly and easily removable redundancy and passivation layers upon lithography and plasma etching in a plasma containing Cl2, the bond structure comprises: a liner or low... | 03/15/2005 |
| 6787908 | Pad metallization over active circuitry Metal bond pads are formed over active circuitry in a semiconductor chip in a reliable and cost effective manner. According to an example embodiment of the present invention, a metal bond pad is formed over circuitry in the semiconductor chip. A metal layer is forme... | 09/07/2004 |
| 6649995 | Semiconductor device and method of manufacturing the same A Schottky diode that achieves a predetermined reverse-direction breakdown voltage even if a state of a surface in a vicinity of a Schottky junction interface changes due to a welding of a bonding wire. The semiconductor device having the Schottky junctio... | 11/18/2003 |
| 6624517 | Low-resistance contact to silicon having a titanium silicide interface and an amorphous titanium carbonitride barrier layer This invention constitutes a contact structure incorporating an amorphous titanium nitride barrier layer formed via low-pressure chemical vapor deposition (LPCVD) utilizing tetrakis-dialkylamido-titanium, Ti(NMe2)4, as the precursor.... | 09/23/2003 |
| 6528817 | Semiconductor device and method for testing semiconductor device A semiconductor device having at least three independently accessible memories, with at least one of the memories having a different memory capacity than the others. Separate selection signals are provided to the memories so that they can be independently... | 03/04/2003 |
| 6448652 | Interconnect structure with a dielectric layer conforming to the perimeter of a wiring layer A first interlayer insulating film and an etching stopper film are sequentially formed on a semiconductor substrate with a surface area on which first wiring is formed. The etching stopper film is patterned so as to correspond to a pattern of via hole for... | 09/10/2002 |
| 6437372 | Diffusion barrier spikes for III-V structures A diffusion preventing barrier spike is disclosed. The spike prevents diffusion of dopants into another layer without forming a pn junction in the layer. The spikes are illustratively Al or an aluminum containing material such as AlAs and have a thickness... | 08/20/2002 |
| 6417564 | Semiconductor element with metal layer The invention relates to a semiconductor element which comprises a metal layer with gold and germanium. A thin covering layer of germanium oxide lies on the metal layer, protecting the subjacent metal layer from undesirable oxidation of the germanium. The... | 07/09/2002 |
| 6400026 | Semiconductor device with the copper containing aluminum alloy bond pad on an active region In a semiconductor device, an active region is formed on a semiconductor substrate. An electrode layer is directly formed on the active region and serves as a bonding pad. The electrode layer is mainly formed by an Al alloy layer containing Cu.... | 06/04/2002 |
| 6362526 | Alloy barrier layers for semiconductors A semiconductor barrier layer and manufacturing method therefor for copper interconnects which is a tantalum-titanium, tantalum-titanium nitride, tantalum-titanium sandwich. The tantalum in the tantalum-titanium alloy bonds strongly with the semiconductor... | 03/26/2002 |
| 6297535 | Transistor having a gate dielectric which is substantially resistant to drain-side hot carrier injection A transistor fabrication process is provided which derives a benefit from having barrier atoms incorporated in a lateral area under a gate oxide of the transistor in close proximity to the drain. To form the transistor, a gate oxide layer is first grown a... | 10/02/2001 |
| 6222267 | Semiconductor device and manufacturing thereof A semiconductor device has: a silicon substrate; a plurality of impurity doped regions formed in a surface layer of the silicon substrate; contact layers each in contact with a surface of associated one of the plurality of impurity doped regions, the cont... | 04/24/2001 |
| 6197628 | Ruthenium silicide diffusion barrier layers and methods of forming same A method for use in the fabrication of integrated circuits includes providing a substrate assembly having a surface. A diffusion barrier layer is formed over at least a portion of the surface. The diffusion barrier layer is formed of RuSix, whe... | 03/06/2001 |
| 6165917 | Passivation of copper with ammonia-free silicon nitride and application to TFT/LCD A method for passivating copper, aluminum, or other refractory metal films using ammonia-free silicon nitride and structures produced by the method. A thin film transistor for use in a liquid crystal display and a method of constructing the same, wherein ... | 12/26/2000 |
| 6130481 | Semiconductor integrated circuit interconnection structures and method of making the interconnection structures A semiconductor integrated circuit structure includes a semiconductor substrate; an electronic element disposed in the substrate; a first electrically insulating layer disposed on the substrate and the electronic element; a first electrically conducting i... | 10/10/2000 |
| 6111298 | Etch stop layer formed within a multi-layered gate conductor to provide for reduction of channel length A process is provided for forming a transistor gate conductor having an etch stop arranged at a depth below its upper surface such that the lateral width of the gate conductor above the etch stop may be exclusively narrowed to provide for reduction of tra... | 08/29/2000 |
| 6093966 | Semiconductor device with a copper barrier layer and formation thereof A method of forming a semiconductor device by first providing a substrate in a processing chamber. The substrate has an insulating layer and an opening in the insulating layer. A copper barrier layer is formed on the insulating layer and in the opening by... | 07/25/2000 |
| 6081034 | Low-resistance contact to silicon having a titanium silicide interface and an amorphous titanium carbonitride barrier layer This invention constitutes a contact structure incorporating an amorphous titanium nitride barrier layer formed via low-pressure chemical vapor deposition (LPCVD) utilizing tetrakis-dialkylamido-titanium, Ti(NMe2)4, as the precursor.... | 06/27/2000 |
| 6056392 | Method of producing recording head A recording head has a liquid emission section with an orifice for emitting ink, an electro-thermal transducer producing thermal energy for ink emission and a functional element electrically connected to the electro-thermal transducer. The functional elem... | 05/02/2000 |
| 6040604 | Semiconductor component comprising an electrostatic-discharge protection device A semiconductor component (10) includes a substrate (11), doped regions (15, 20) in the substrate (11), interconnect layers (23, 26, 29) coupled to one of the doped layers, and dielectric layers (21, 24, 27) between the interconnect layers (23, 26, 29) wh... | 03/21/2000 |
| 5952721 | Semiconductor device having oxygen-doped silicon layer so as to restrict diffusion from heavily doped silicon layer A phosphorous doped amorphous silicon storage node electrode is treated with heat so as to be converted into a phosphorous doped polysilicon storage electrode, and the heat causes the phosphorous to be diffused into a shallow n-type source region of an n-... | 09/14/1999 |
| 5939787 | Semiconductor device having a multi-layer contact structure A semiconductor device and manufacturing method thereof having a diffusion barrier layer formed on a semiconductor wafer, whose surface region is provided with a silylation layer, wherein the silylation layer is formed on the diffusion barrier layer which... | 08/17/1999 |
| 5852328 | Semiconductor device and method of manufacturing the same After forming a first wire on a first interlayer insulation film, a second interlayer insulation film is formed and planarized, to thereby form a via hole. At this stage, the via hole is formed off the first wire. Next, after making an exposed edge and an... | 12/22/1998 |
| 5831283 | Passivation of copper with ammonia-free silicon nitride and application to TFT/LCD A layer for passivating copper, aluminum, or other refractory metal films using ammonia-free silicon nitride and structures produced by the method. A thin film transistor for use in a liquid crystal display, wherein the transistor has a gate, a source and... | 11/03/1998 |
| 5760476 | Interconnect run between a first point and a second point in a semiconductor device for reducing electromigration failure In a first approach, an interconnect structure (10) reduces peak localized interconnect current density by distributing current flow around the perimeter (22) of an interlevel connector (14) in a semiconductor device. A first interconnect level (12) is co... | 06/02/1998 |
