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| Number | Title | Issue Date |
| 7256484 | Memory expansion and chip scale stacking system and method The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. In another aspect, the invention provides a lower capacitance memory expansion addressing system and method and preferably with th... | 08/14/2007 |
| 7256069 | Wafer-level package and methods of fabricating A carrier for use in a chip-scale package, including a polymeric film with apertures defined therethrough. The apertures, which are alignable with corresponding bond pads of a semiconductor device, each include a quantity of conductive material extending substantial... | 08/14/2007 |
| 7253510 | Ball grid array package construction with raised solder ball pads The present invention provides for a BGA solder ball interconnection to an outer conductive layer of a laminated circuit assembly having an underlying circuit layer. The invention includes a raised BGA solder ball pad substantially co-planar with the outer conductiv... | 08/07/2007 |
| 7253088 | Stress-relief layers and stress-compensation collars with low-temperature solders for board-level joints, and processes of making same A stress-relief layer is formed by dispensing a polymer upon a substrate lower surface under conditions to partially embed a low melting-point solder bump that is disposed upon the lower surface. The stress-relief layer flows against the low melting-point solder bum... | 08/07/2007 |
| 7253503 | Integrated circuit device packages and substrates for making the packages Integrated circuit device packages and substrates for making the packages are disclosed. One embodiment of a substrate includes a planar sheet of polyimide having a first surface, an opposite second surface, and apertures between the first and second surfaces. A pla... | 08/07/2007 |
| 7253504 | Integrated circuit package and method An integrated circuit package includes a substrate having a central axis dividing the substrate into an upper half and a lower half and an integrated circuit coupled to the substrate. A layer is provided within the substrate in the lower half thereof that is configu... | 08/07/2007 |
| 7253519 | Chip packaging structure having redistribution layer with recess A chip structure comprising a chip, a redistribution layer, a second passivation layer and at least a bump is provided. The chip has a first passivation layer and at least a bonding pad. The first passivation layer exposes the bonding pad and has at least a recess. ... | 08/07/2007 |
| 7253505 | IC substrate with over voltage protection function The present invention relates to an IC substrate provided with over voltage protection functions and thus, a plurality of over voltage protection devices are provided on a single substrate to protect an IC chip directly. According to the present invention, there is ... | 08/07/2007 |
| 7253520 | CSP semiconductor device having signal and radiation bump groups A semiconductor device comprises a semiconductor chip which has a first surface, a pad which is formed directly on the first surface, an oxide film which is formed on the first surface, an insulating film which is formed on the oxide film and a part of the pad, a co... | 08/07/2007 |
| 7253078 | Method and apparatus for forming an underfill adhesive layer An apparatus and method for forming a layer of underfill adhesive on an integrated circuit in wafer form is described. In one embodiment, the layer of underfill adhesive is disposed and partially cured on the active surface of the wafer. Once the underfill adhesive ... | 08/07/2007 |
| 7250576 | Chip package having chip extension and method A chip package including a chip extension for containing thermal interface material (TIM) and improves chip cooling, and a related method, are disclosed. In particular, the chip package includes a chip, a cooling structure coupled to the chip via a TIM, and a chip e... | 07/31/2007 |
| 7250659 | Semiconductor component with ESD protection The semiconductor component has ESD protective elements configured outside the semiconductor body. The ESD protective elements connect an additional conductor track that carries a reference potential to conductor tracks of the leadframe. ESD protective structures in... | 07/31/2007 |
| 7250673 | Signal isolation in a package substrate Signal traces are patterned on a top surface of a substrate. A ground trace is patterned on the top surface of the substrate for at least one pair of the signal traces. A die paddle is patterned on the top surface of the substrate, and the die paddle is connected di... | 07/31/2007 |
| 7250678 | Copper-containing C4 ball-limiting metallurgy stack for enhanced reliability of packaged structures and method of making same The invention relates to a ball-limiting metallurgy stack for an electrical device that contains at least one copper layer disposed upon a Ti adhesion metal layer. The ball-limiting metallurgy stack resists Sn migration toward the upper metallization of the device. | 07/31/2007 |
| 7247951 | Chip carrier with oxidation protection layer A chip carrier comprising a laminated layer and an oxidation protection layer is provided. The oxidation protection layer is a non-electrolytic metallic coating or an organic oxidation protection film on the surface of bonding finger pads or other contacts formed by... | 07/24/2007 |
| 7247947 | Semiconductor device comprising a plurality of semiconductor constructs A semiconductor device includes a first semiconductor construct provided on a base plate and having a semiconductor substrate and external connection electrodes. An insulating layer is provided on the base plate around the first semiconductor construct. An upper lay... | 07/24/2007 |
| 7247516 | Method for fabricating a leadless chip carrier Structure and method for fabrication of a leadless chip carrier have been disclosed. A disclosed embodiment comprises a substrate having a top surface for receiving a semiconductor die. The disclosed embodiment also comprises a printed circuit board attached to a bo... | 07/24/2007 |
| 7247518 | Semiconductor device and method for manufacturing same There is provided a semiconductor device of a chip-on-chip structure having a support semiconductor chip, first and second chip blocks supported and connected on one surface of the support semiconductor chip and an insulator arranged between the first and second chi... | 07/24/2007 |
| 7247932 | Chip package with capacitor A chip package for semiconductor chips is provided by the method of forming a chip package includes the steps of forming a printed circuit board with a window therethrough; forming semiconductor chip connections of one or more primary chips which overlie the window ... | 07/24/2007 |
| 7247945 | Semiconductor apparatus A semiconductor apparatus includes a printed circuit board, a peripheral type first semiconductor package which has a first group of ball electrodes arranged in a peripheral type first arrangement area and a first group of additional ball electrodes arranged inside ... | 07/24/2007 |
| 7247934 | Multi-chip semiconductor package A multi-chip semiconductor package and a fabrication method thereof are provided. At least one first chip is mounted on and electrically connected to an upper surface of a substrate via solder bumps. A preformed package structure having a second chip and a first enc... | 07/24/2007 |
| 7246432 | Method of manufacturing semiconductor device A method of manufacturing a semiconductor device includes (a) forming a first resin layer on a semiconductor substrate including an electrode pad and a passivation film, (b) curing the first resin layer, (c) forming a second resin layer which slopes more gently than... | 07/24/2007 |
| 7245022 | Semiconductor module with improved interposer structure and method for forming the same Under the present invention, a semiconductor chip is electrically connected to a substrate (e.g., organic, ceramic, etc.) by an interposer structure. The interposer structure comprises an elastomeric, compliant material that includes metallurgic through connections ... | 07/17/2007 |
| 7244633 | Chip carrier substrate with a land grid array and external bond terminals A carrier for a semiconductor die has a substrate with a cavity formed in the substrate. The cavity has a bottom and sidewalls, and the sidewalls have a stepped tier. Electrically conductive contacts are disposed on an underside of the substrate. Electrically conduc... | 07/17/2007 |
| 7245477 | Decoupling capacitor and method A capacitor having a first nickel electrode. A BCTZ dielectric covers a side of the first nickel electrode. A second nickel electrode sandwiches the BCTZ. ... | 07/17/2007 |
| 7245013 | Substrate based IC-package A semiconductor component comprises a substrate that includes wiring on a first surface. A chip is mounted on a second surface of the substrate by a die attach, the second surface opposite the first surface. A bond channel in the center of the substrate allows for e... | 07/17/2007 |
| 7245506 | System for reducing noise induced from reference plane currents A method of reducing noise induced from reference plane currents is disclosed. The method includes routing a first path for an electrical trace on a circuit board such that the first path references a voltage plane. The method further includes routing a second path ... | 07/17/2007 |
| 7242099 | Chip package with multiple chips connected by bumps A method of assembling chips. A first chip and a second chip are provided. At least one conductive pillar is formed on the first chip, and a conductive connecting material is formed on the conductive pillar. The second chip also comprises at least one conductive pil... | 07/10/2007 |
| 7242097 | Electromigration barrier layers for solder joints A microelectronic package is disclosed including a microelectronic device, a substrate, and a signaling path coupling the microelectronic device with the substrate. The signaling path includes a conductive material, a solder joint, and a barrier material disposed be... | 07/10/2007 |
| 7238551 | Method of fabricating semiconductor package including die interposed between cup-shaped lead frame having mesas and valleys A semiconductor package includes a die that is interposed, flip-chip style, between an upper lead frame and a lower lead frame. The lower lead frame has contacts that are aligned with terminals on the bottom surface of the die. The upper lead frame contacts a termin... | 07/03/2007 |
| 7238891 | Circuit board with at least one rigid and at least one flexible area and process for producing rigid-flexible circuit boards A rigid-flexible circuit board with two rigid areas and one flexible area, with a rigid individual layer which is copper-clad on one side, with an adhesive medium and with a copper foil, the adhesive medium having recesses in the flexible area. The rigid-flexible ci... | 07/03/2007 |
| 7239028 | Semiconductor device with signal line having decreased characteristic impedance A semiconductor device includes a semiconductor chip, electrodes pads, an insulating layer, first and second conductive patterns and external terminals. The electrode pads are formed on a first area of a main surface of the semiconductor chip. The insulating layer i... | 07/03/2007 |
| 7239024 | Semiconductor package with recess for die A semiconductor package is disclosed with a recess (51) for an integrated circuit die (52). The recess is made by bending or deforming all layers of a package substrate, and therefore the recess contains circuitry to connect to the integrated circuit d... | 07/03/2007 |
| 7239027 | Bonding structure of device packaging A bonding structure of device packaging includes a first substrate and a second substrate. The surfaces of the first substrate have metal pads and a first bonding layer connected to the second substrate whose surfaces have a second bonding layer and electrodes. The ... | 07/03/2007 |
| 7239023 | Package assembly for electronic device A buffer layer is formed on a substrate and then electronic devices are packed on the buffer layer in the present invention, and problems of lower hermeticity and complex process in the conventional arts can be avoided. Therefore, the present invention provides a pa... | 07/03/2007 |
| 7234359 | Semiconductor force sensor A semiconductor force sensor capable of preventing a diaphragm part (37) from being broken and accurately measuring a force applied thereto in a direction orthogonal to the diaphragm part (37), wherein a force transmitting means for applying a measured... | 06/26/2007 |
| 7235886 | Chip-join process to reduce elongation mismatch between the adherents and semiconductor package made thereby A chip-join process to reduce elongation mismatch between the adherents involves thermally expanding each of a coefficient of thermal expansion mismatched semiconductor chip and substrate a substantially equal amount from their room temperature state in a direction ... | 06/26/2007 |
| 7235881 | Electronic component, semiconductor device, methods of manufacturing the same, circuit board, and electronic instrument The present invention is a semiconductor device capable of relieving thermal stress without breaking wire. It comprises a semiconductor chip (12), a solder ball (20) for external connection, wiring (18) for electrically connecting the semiconduc... | 06/26/2007 |
| 7235426 | Method of backside grinding a bumped wafer A method for backside grinding a bumped wafer is disclosed. A wafer has a plurality of bumps formed on the active surface thereof. Prior to grinding the back surface of the wafer, a hot-melt adhesive layer is formed on the active surface of the wafer so as to be adh... | 06/26/2007 |
| 7235870 | Microelectronic multi-chip module A method of fabricating a microelectronic multi-chip module comprises: providing a cavity down ball grid array having a die and solder balls on a die side thereof; providing a package including at least one die thereon on a die side thereof; stacking the package ont... | 06/26/2007 |
