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| Number | Title | Issue Date |
| 7215022 | Multi-die module A multi-die module is electrically connected to both an unpackaged die and a packaged die as disclosed herein. The multi-die module has a footprint that is the same as conventional multi-die packages, which do not include packaged die, thereby allowing the multi-die... | 05/08/2007 |
| 7215030 | Lead-free semiconductor package A package substrate includes die solder pads and pin solder fillets. The pin solder fillets might comprise between approximately 90 wt % to approximately 99 wt % tin and approximately 10 wt % to 1 wt % antimony. The die solder pads might comprise between approximate... | 05/08/2007 |
| 7213331 | Method for forming stencil A method of forming a stencil for the manufacture of semiconductor devices includes defining a plurality of slightly spaced segmental annular openings in a stencil plate. The spacing between the segmental annular openings define spokes extending from a central porti... | 05/08/2007 |
| 7214569 | Apparatus incorporating small-feature-size and large-feature-size components and method for making same An apparatus incorporating small-feature size and large-feature-size components. The apparatus comprise a strap including a substrate with an integrated circuit contained therein. The integrated circuit coupling to a first conductor disposed on the substrate. The fi... | 05/08/2007 |
| 7211892 | Semiconductor device having a particular electrode structure In order to inhibit the connection failure due to the degradation of the connection interface strength of the electrode pad and the warp thereof in the semiconductor device having an electrode pad, a metal layer formed on the electrode pad, and a metal bump formed o... | 05/01/2007 |
| 7211901 | Self-coplanarity bumping shape for flip chip A stud bump structure for electrical interconnection between a pair of members includes a base portion, and a stem portion. The base portion is affixed to a pad or trace in one of the pair of members to be interconnected (such as an integrated circuit chip), and the... | 05/01/2007 |
| RE39603 | Process for manufacturing semiconductor device and semiconductor wafer A process for manufacturing a semiconductor device includes defining chip sections on a wafer by scribe lines with each chip section having chip electrodes formed thereon. The wafer is covered with a passivating film except for on the chip electrodes. Aluminum inter... | 05/01/2007 |
| 7211893 | Integrating chip scale packaging metallization into integrated circuit die structures Wafer-level chip-scale packaging technology is used for improving performance or reducing size of integrated circuits by using metallization of pad-to-bump-out beams as part of the integrated circuit structure. Chip-scale packaging under bump metal is routed to incr... | 05/01/2007 |
| 7212013 | Apparatus for measuring parasitic capacitance and inductance of I/O leads on an electrical component using a network analyzer Apparatus and methods are provided for measuring the potential for mutual coupling in an integrated circuit package of any type or configuration using a network analyzer in conjunction with a coaxial test probe. Simple, low-cost test fixturing and methods of testing... | 05/01/2007 |
| 7211894 | Capacitor-related systems for addressing package/motherboard resonance According to some embodiments, a device includes a first conductive plane electrically coupled to a first terminal associated with a first polarity and a second terminal associated with the first polarity, a second conductive plane electrically coupled to a third te... | 05/01/2007 |
| 7208835 | Integrated circuit package and assembly thereof An integrated circuit (IC) package and IC assembly. The IC assembly comprises the IC package, an insulating substrate and an adhesive film. The IC package comprises a chip body and a plurality of bumps. The bumps are disposed on a first surface of the chip body, eac... | 04/24/2007 |
| 7208839 | Semiconductor component assemblies having interconnects Methods relating to forming interconnects through injection of conductive materials, to fabricating semiconductor component assemblies, and to resulting assemblies. A semiconductor component substrate, such as a semiconductor die or other substrate, has dielectric m... | 04/24/2007 |
| 7209356 | Heat dissipation device A heat dissipation device includes a first heat sink (10) mounted on one side of a video graphics adapter (VGA) card (70) on which a heat generating componnent is mounted to dissipate heat generated by the heat generating componnent, a second heat sink... | 04/24/2007 |
| 7208833 | Electronic circuit device having circuit board electrically connected to semiconductor element via metallic plate An electronic circuit device comprises: a semiconductor element having a first surface and a second surface, with the first and second surfaces being on first and second sides of the semiconductor element, respectively, and facing in opposite directions; a first ele... | 04/24/2007 |
| 7208824 | Land grid array module Disclosed is a land grid array module comprising: a substrate; a plurality of active and passive components mounted on both sides of the substrate; and a molding compound for encapsulating the both sides of the substrate with the active and passive components mounte... | 04/24/2007 |
| 7208825 | Stacked semiconductor packages A semiconductor package and a fabrication method thereof are provided in which a chip is mounted on a substrate, and a dielectric layer is applied over the substrate and chip, with bond fingers formed on the substrate and electric contacts formed on the chip being e... | 04/24/2007 |
| 7208402 | Method and apparatus for improved power routing An apparatus comprising: a die having a top metal layer, the top metal layer comprised of at least a first metal line and a second metal line; a passivation layer covering the top metal layer; a C4 bump on the passivation layer; and a first passivation opening and a... | 04/24/2007 |
| 7205649 | Ball grid array copper balancing A ball grid array device includes a substrate having a first major surface and a second major surface. The first major surface includes leads for electrical connections. The second major surface is devoid of leads. The ball grid array device also includes a first la... | 04/17/2007 |
| 7205673 | Reduce or eliminate IMC cracking in post wire bonded dies by doping aluminum used in bond pads during Cu/Low-k BEOL processing A bond pad structure which includes an aluminum bond pad which include one or more dopants that effectively control the growth of IMC to a nominal level in spite of high tensile stresses in the wafer. For example, aluminum can be doped with 1–2 atomic % of Mg. Alt... | 04/17/2007 |
| 7205646 | Electronic device and chip package The package includes a substrate, a first chip, a second chip, multiple first bumps and multiple second bumps. The substrate has a first region and a second region. The first region is substantially coplanar with the second region. The first bumps connect the first ... | 04/17/2007 |
| 7205032 | Controlled thermal expansion of welds to enhance toughness A method is provided for forming a metallic overlay having enhanced toughness. The metallic overlay may be a weld, a metallic coating, or similar application. The method includes applying a glass forming metallic alloy to a substrate while the alloy is in a molten o... | 04/17/2007 |
| 7205648 | Flip-chip light emitting diode package structure A flip-chip LED package structure is disclosed. The flip-chip LED package structure includes a submount, patterned conductive films, a LED chip and two bumps. Several grooves are formed on the sidewalls of the submount. The patterned conductive films are formed on t... | 04/17/2007 |
| 7205177 | Methods of bonding two semiconductor devices A method of bonding two elements such as wafers used in microelectronics applications is disclosed. One inventive aspect relates to a method for bonding comprising producing on a first main surface of a first element a first solder ball, producing on a first main su... | 04/17/2007 |
| 7205642 | Semiconductor package and method for fabricating the same A semiconductor package and a method for fabricating the same are proposed. A substrate having a first circuit layer, a second circuit layer, and a core layer formed between the first and second circuit layers is provided. At least one second opening is formed on th... | 04/17/2007 |
| 7202555 | Pitch change and chip scale stacking system and method The present invention stacks integrated circuits into modules that conserve board surface area. In a two-high stack or module devised in accordance with a preferred embodiment of the present invention, a pair of integrated circuits is stacked, with one integrated ci... | 04/10/2007 |
| 7202569 | Semiconductor device and manufacturing method of the same A semiconductor device comprises a semiconductor element which is flip-chip bonded to a circuit substrate. The semiconductor element and the circuit substrate are flip-chip bonded using a sealing resin having flux function. The semiconductor element includes a solde... | 04/10/2007 |
| 7202113 | Wafer level bumpless method of making a flip chip mounted semiconductor device package A wafer level bumpless method of making flip chip mounted semiconductor device packages is disclosed. The method includes the steps of solder mask coating a semiconductor die wafer frontside, processing the solder mask coating to reveal a plurality of gate contact a... | 04/10/2007 |
| 7202552 | MEMS package using flexible substrates, and method thereof A MEMS package and a method for its forming are described. The MEMS package has at least one MEMS device located on a flexible substrate. A metal structure surrounds the at least one MEMS device wherein a bottom surface of the metal structure is attached to the flex... | 04/10/2007 |
| 7199459 | Semiconductor package without bonding wires and fabrication method thereof A semiconductor package without bonding wires and a fabrication method are provided. The semiconductor package includes a substrate having a front surface and a back surface, two chips formed on the front surface, two dielectric layers formed on the chips respective... | 04/03/2007 |
| 7199475 | Semiconductor copper bond pad surface protection Electronic packages with uninsulated portions of copper circuits protected with coating layers having thicknesses that are suitable for soldering without fluxing and are sufficiently frangible when being joined to another metal surface to obtain metal-to-metal conta... | 04/03/2007 |
| 7199593 | Apparatus and methods for measuring parasitic capacitance and inductance of I/O leads on an electrical component using a network analyzer Apparatus and methods are provided for measuring the potential for mutual coupling in an integrated circuit package of any type or configuration using a network analyzer in conjunction with a coaxial test probe. Simple, low-cost test fixturing and methods of testing... | 04/03/2007 |
| 7199037 | Microfeature devices and methods for manufacturing microfeature devices Microfeature devices, microfeature workpieces, and methods for manufacturing microfeature devices and microfeature workpieces are disclosed herein. The microfeature workpieces have an integrated circuit, a surface, and a plurality of interconnect elements projecting... | 04/03/2007 |
| 7196427 | Structure having an integrated circuit on another integrated circuit with an intervening bent adhesive element Two or more semiconductor packages are stacked with an intervening element that is positioned between within an area surrounded by conductive bumps of a bottom surface of the overlying package. Different shapes of the intervening element are used depending upon how ... | 03/27/2007 |
| 7196001 | Copper-containing C4 ball-limiting metallurgy stack for enhanced reliability of packaged structures and method of making same The invention relates to a ball-limiting metallurgy stack for an electrical device that contains at least one copper layer disposed upon a Ti adhesion metal layer. The ball-limiting metallurgy stack resists Sn migration toward the upper metallization of the device. | 03/27/2007 |
| 7192810 | Semiconductor packaging An electronic component and a method for making an electronic component are disclosed. The electronic component has a silicon package. The silicon package has a recess formed thereon in which a conductive region is placed. A bare die electronic device is disposed in... | 03/20/2007 |
| 7193329 | Semiconductor device The semiconductor device includes a tabular base metal having an insulating layer provided on a bottom surface thereof, and the insulating layer includes a plurality of wiring patterns, each of which is provided with a connecting pad at one end thereof. A semiconduc... | 03/20/2007 |
| 7192861 | Wire bonding for thin semiconductor package An assembly of a semiconductor chip (301) having an integrated circuit (IC) including at least one contact pad (320) on its surface (301a), wherein the contact pad has a metallization suitable for wire bonding, and an interconnect bonded ... | 03/20/2007 |
| 7192867 | Protection of low-k dielectric in a passivation level In one embodiment, a passivation level includes a low-k dielectric. To prevent the low-k dielectric from absorbing moisture when exposed to air, exposed portions of the low-k dielectric are covered with spacers. As can be appreciated, this facilitates integration of... | 03/20/2007 |
| 7192870 | Semiconductor device and fabrication process therefor A semiconductor device which includes: a semiconductor chip bonded to a surface of a solid device; and a stiffener surrounding the periphery of the semiconductor chip. A surface of the stiffener opposite from the solid device is generally flush with a surface of the... | 03/20/2007 |
| 7193311 | Multi-chip circuit module and method for producing the same A multi-chip circuit module on which semiconductor chips are loaded and which is provided with circuit patterns, input/output terminals or the like for interconnecting the semiconductor chips. A multi-layered wiring section (2) is formed by respective unit wi... | 03/20/2007 |
