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| Number | Title | Issue Date |
| 7223636 | Manufacturing method of semiconductor device and semiconductor device In a dividing method according to the present invention, a wiring board formed of ceramic is forced up (upper swing) by a lower clamp claw of a clamper, and some of a protruded wiring board portion protruding from a conveying chute is pressed against a support body ... | 05/29/2007 |
| 7223681 | Interconnection pattern design An interconnection pattern design, which has an improved reliability under mechanical shock and thermal cycling loads. A semiconductor component comprises a plurality of interconnections aligned into rows and columns to form an interconnection pattern, wherein the i... | 05/29/2007 |
| 7224053 | Semiconductor device responsive to different levels of input and output signals and signal processing system using the same A semiconductor device which integrates a plurality of semiconductor chips into a single package includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip includes a plurality of first bonding pads outputting first signals hav... | 05/29/2007 |
| 7224054 | Semiconductor device and system having semiconductor device mounted thereon A ball grid array packaged semiconductor device mounted on a mounting board and including pads formed within a package and are connected to signal lines of a bare chip by bonding wires. There are formed first vias extending from the respective pads to a bottom surfa... | 05/29/2007 |
| 7221048 | Multilayer circuit carrier, panel, electronic device, and method for producing a multilayer circuit carrier A multilayer circuit carrier, electronic devices and panel, and a method for producing a multilayer circuit carrier include at least one semiconductor chip, at least one rewiring layer with a rewiring structure, and at least one insulation layer, which has passage s... | 05/22/2007 |
| 7218008 | Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument A semiconductor device includes: a semiconductor substrate in which an integrated circuit is formed; an interconnect layer which includes a linear section and a land section connected with the linear section; and an underlayer disposed under the interconnect layer, ... | 05/15/2007 |
| 7217997 | Ground arch for wirebond ball grid arrays A structure provides for the control of bond wire impedance. In an example embodiment, there is an integrated circuit device comprising a semiconductor device die having a plurality of grounding pads, signal pads, and power pads and a package for mounting the integr... | 05/15/2007 |
| 7213329 | Method of forming a solder ball on a board and the board In the method, a conductive pad of the board is etched to a depth that is greater than 50% and less than 100% of a thickness of the conductive pad. Subsequently, a solder ball may be formed on the etched conductive pad. For example, the conductive pad may be copper.... | 05/08/2007 |
| 7215026 | Semiconductor module and method of forming a semiconductor module In one embodiment, a semiconductor module includes at least one semiconductor chip package, a board having functional pads and dummy pads, and at least one solder joint electrically connecting the semiconductor chip package and one of the functional pads of the boar... | 05/08/2007 |
| 7214887 | Electronic circuit connecting structure, and its connecting method A connecting structure includes a circuit board with a first connection land having a plurality of conductor patterns on the surface thereof, a second connection land disposed in a position opposite to the first connection land of the circuit board, and a flexible b... | 05/08/2007 |
| 7211903 | Semiconductor device and manufacturing method of them A semiconductor device which can meet the requirement for a further increase in pins, which multi-functionalization and faster operation would entail is to be provided. Bonding pads and bonding pads are arranged in a zigzag pattern in a direction along an outer circ... | 05/01/2007 |
| 7211883 | Semiconductor chip package A semiconductor chip package is formed by a first semiconductor chip and a second semiconductor chip, which have electrodes for wiring at surfaces thereof, being integrated and mounted in a state in which reverse surfaces thereof oppose one another. Therefore, two s... | 05/01/2007 |
| 7211887 | connection arrangement for micro lead frame plastic packages A connection arrangement for a micro lead frame plastic (MLP) package is provided that includes a paddle configured to be connected to a circuit board and a first ground pad and a second ground pad each connected to the paddle. The first and second ground pads toget... | 05/01/2007 |
| 7211510 | Stacking circuit elements A method of stacking dice in an electronic circuit includes controlling a size of a hole made in a connection pad on each die of said dice to selectively provide an electrical connection to a particular die in the stack. Additionally, a method of stacking dice in an... | 05/01/2007 |
| 7211500 | Pre-process before cutting a wafer and method of cutting a wafer A pre-process before cutting a wafer is described. The wafer includes a plurality of scribe lines and a plurality of dies defined by the scribe lines, and a material layer covers the wafer. A pre-processing step is performed to remove the material layer on the scrib... | 05/01/2007 |
| 7211900 | Thin semiconductor package including stacked dies A semiconductor package and method for fabricating the same is disclosed. In one embodiment, the semiconductor package includes a circuit board, at least two semiconductor chips, electric connection means, an encapsulant, and a plurality of conductive balls. The cir... | 05/01/2007 |
| 7208840 | Semiconductor module, electronic device and electronic equipment, and method for manufacturing semiconductor module First alignment marks are provided on a film substrate in a manner that they are located at positions offset from the disposed positions of second alignment marks provided on a semiconductor chip. The amount of expansion or contraction of the film substrate is obtai... | 04/24/2007 |
| 7208833 | Electronic circuit device having circuit board electrically connected to semiconductor element via metallic plate An electronic circuit device comprises: a semiconductor element having a first surface and a second surface, with the first and second surfaces being on first and second sides of the semiconductor element, respectively, and facing in opposite directions; a first ele... | 04/24/2007 |
| 7208829 | Semiconductor component A semiconductor component that is able to be produced simply, quickly, and yet reliably and that usable for power applications, and including a semiconductor chip, a lower, first main electrode layer formed on a first side of the semiconductor chip, a lower control ... | 04/24/2007 |
| 7208830 | Interconnect shunt used for current distribution and reliability redundancy In one embodiment of the invention, an integrated circuit package includes an integrated circuit, a package substrate, a first bump, a second bump and a shunt to provide for current distribution and reliability redundancy. The first and second bumps provide a first ... | 04/24/2007 |
| 7208820 | Substrate having a plurality of I/O routing arrangements for a microelectronic device A substrate is provided for packaging a microelectronic device having a pattern of contacts on the surface thereof. The substrate is formed from a support member having a substantially planar surface, and first, second, and third electrically conductive paths. The e... | 04/24/2007 |
| 7205649 | Ball grid array copper balancing A ball grid array device includes a substrate having a first major surface and a second major surface. The first major surface includes leads for electrical connections. The second major surface is devoid of leads. The ball grid array device also includes a first la... | 04/17/2007 |
| 7205668 | Multi-layer printed circuit board wiring layout A multi-layer printed circuit board (PCB) includes a first wire layer, a middle layer above the first wire layer, a second wire layer above the middle layer, and a slanting via formed in the middle layer and the second wire layer. The manufacturing method includes t... | 04/17/2007 |
| 7205673 | Reduce or eliminate IMC cracking in post wire bonded dies by doping aluminum used in bond pads during Cu/Low-k BEOL processing A bond pad structure which includes an aluminum bond pad which include one or more dopants that effectively control the growth of IMC to a nominal level in spite of high tensile stresses in the wafer. For example, aluminum can be doped with 1–2 atomic % of Mg. Alt... | 04/17/2007 |
| 7206515 | Single-ended/differential wired radio frequency interface A package to encapsulate an optical component includes a RF interface to receive high frequency signals from an external source. The RF interface pins that can be configured as one or more single-ended transmission lines or as one or more differential transmission l... | 04/17/2007 |
| 7204017 | Manufacturing method of a modularized leadframe A manufacturing method of a modularized leadframe, using a first mold set to contact and hold the upper surface of rows of multiple block leads, using a second mold set to contact and hold at least one selected surface of the lower surface of leads, the second mold ... | 04/17/2007 |
| 7205180 | Process of fabricating semiconductor packages using leadframes roughened with chemical etchant A semiconductor package contains a metal leadframe that has been specially treated by roughening it with a chemical etchant. The roughening process enhances the adhesion between the leadframe and the molten plastic during the encapsulation of the leadframe and there... | 04/17/2007 |
| 7206918 | Address predicting apparatus and methods Apparatus and methods for addressing predicting useful in high-performance computing systems. The present invention provides novel correlation prediction tables. In one embodiment, correlation prediction tables of the present invention contain an entered key for eac... | 04/17/2007 |
| 7205638 | Silicon building blocks in integrated circuit packaging An improved silicon building block is disclosed. In an embodiment, the silicon building block has at least two vias through it. The silicon building block is doped and the vias filled with a first material, and, optionally, selected ones of the vias filled instead w... | 04/17/2007 |
| 7202566 | Crossed power strapped layout for full CMOS circuit design An integrated circuit device and method thereof includes a substrate and a plurality of microelectronic devices. Each of the microelectronics devices includes a patterned feature located over the substrate, wherein the pattern feature comprises at least one electric... | 04/10/2007 |
| 7202105 | Multi-chip semiconductor connector assembly method In one exemplary embodiment, a multi-chip connector is formed to have a first conductive strip that is attached to a first semiconductor die and a second conductive strip that is attached to a second semiconductor die. ... | 04/10/2007 |
| 7202545 | Memory module and method for operating a memory module A memory module has an electronic printed circuit board and a plurality of semiconductor memory chips. A series circuit of the semiconductor memory chips is formed with the aid of two leads that can be driven by external contacts of the printed circuit board, and wi... | 04/10/2007 |
| 7199459 | Semiconductor package without bonding wires and fabrication method thereof A semiconductor package without bonding wires and a fabrication method are provided. The semiconductor package includes a substrate having a front surface and a back surface, two chips formed on the front surface, two dielectric layers formed on the chips respective... | 04/03/2007 |
| 7199453 | Semiconductor package and fabrication method thereof A semiconductor package and a fabrication method thereof are proposed. A lead frame is provided between a chip and a substrate in a window ball grid array semiconductor package, wherein an active surface of the chip is electrically connected to the lead frame via bo... | 04/03/2007 |
| 7198969 | Semiconductor chip assemblies, methods of making same and components for same Semiconductor chip assemblies incorporating flexible, sheet-like elements having terminals thereon overlying the front or rear face of the chip to provide a compact unit. The terminals on the sheet-like element are movable with respect to the chip, so as to compensa... | 04/03/2007 |
| 7199455 | Molded resin semiconductor device having exposed semiconductor chip electrodes A semiconductor chip and a wiring strip are placed on a flat side of a base sheet. The semiconductor chip has parallel first and second surfaces. Electrodes are connected to the first surface. The electrodes all terminate in the plane of the flat side of the base sh... | 04/03/2007 |
| 7199452 | Semiconductor device and manufacturing method for same A semiconductor device in which semiconductor chip(s) is or are mounted onto substrate(s) incorporating patterned wiring and the entirety or entireties has or have been sealed with resin(s), wherein by forming electrically conductive pattern(s) for shielding at end ... | 04/03/2007 |
| 7199593 | Apparatus and methods for measuring parasitic capacitance and inductance of I/O leads on an electrical component using a network analyzer Apparatus and methods are provided for measuring the potential for mutual coupling in an integrated circuit package of any type or configuration using a network analyzer in conjunction with a coaxial test probe. Simple, low-cost test fixturing and methods of testing... | 04/03/2007 |
| 7199460 | Semiconductor device and method of manufacturing the same A semiconductor device capable of reducing its size and increasing the number of chips on a wafer, and a method of manufacturing the same are provided. When manufacturing a semiconductor device, an uppermost layer as a dedicated layer for pads are formed above a lay... | 04/03/2007 |
| 7199469 | Semiconductor device having stacked semiconductor chips sealed with a resin seal member The cost of a semiconductor device is to be reduced. An electrical connection between a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip is made through an inner lead portion of a lead disposed at a position around the... | 04/03/2007 |
