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| Number | Title | Issue Date |
| 7728419 | Semiconductor package adapted for high-speed data processing and damage prevention of chips packaged therein and method for fabricating the same A semiconductor package includes a semiconductor chip provided with a first surface having a bonding pad, a second surface opposing to the first surface and side surfaces; a first redistribution pattern connected with the bonding pad and extending along the first su... | 06/01/2010 |
| 7728420 | High current lead electrode for semiconductor device A semiconductor package that includes a lead frame riveted to pillars electrically connect to an electrode of a semiconductor die. ... | 06/01/2010 |
| 7723836 | Chip stack structure having shielding capability and system-in-package module using the same A chip stack structure having a shielding capability may comprise a wiring substrate, the wiring substrate including a ground layer. The structure may also comprise a first chip attached on an upper surface of the wiring substrate and electrically connected to the g... | 05/25/2010 |
| 7719099 | Package structure for solid-state lighting devices and method of fabricating the same Silicon substrates are applied to the package structure of solid-state lighting devices. Wet etching is performed to both top and bottom surfaces of the silicon substrate to form reflecting cavity and electrode access holes. Materials of the reflecting layer and ele... | 05/18/2010 |
| 7714426 | Ball grid array package format layers and structure Layers suitable for stacking in three dimensional, multi-layer modules are formed by interconnecting a ball grid array electronic package to an interposer layer which routes electronic signals to an access plane. The layers are under-filled and may be bonded togethe... | 05/11/2010 |
| 7709945 | Multichip sensor A multichip sensor includes an element chip having a detection element of a sensor; a signal-processing IC chip having a signal-processing IC for processing an output signal of the detection element; and a package adapted to accommodate at least the element chip and... | 05/04/2010 |
| 7705443 | Semiconductor device with lead frame including conductor plates arranged three-dimensionally An electrical connection inside a semiconductor device is established by lead frames formed of plural conductor plates. The lead frames are disposed three-dimensionally so that the respective weld parts thereof are exposed toward a laser light source used in the las... | 04/27/2010 |
| 7701047 | Integrated-circuit chip with offset external pads and method for fabricating such a chip An integrated-circuit chip includes a first electrical connection are placed on an underlying layer and covered with an intermediate dielectric layer. A second electrical connection is placed on the intermediate dielectric layer and is covered with a superficial die... | 04/20/2010 |
| 7692283 | Device including a housing for a semiconductor chip including leads extending into the housing A device including a housing for a semiconductor chip is disclosed. One embodiment provides a plurality of leads. A first lead forms an external contact element at a first housing side and extends at the first housing side into the housing in the direction of an opp... | 04/06/2010 |
| 7692281 | Land grid array module with contact locating features A land grid array module is provided that includes a land grid array interface. The interface includes a substrate having a mating face. A contact pad is provided on the mating face of the substrate. The contact pad has an exposed surface with a depression that is c... | 04/06/2010 |
| 7692282 | Semiconductor device including semiconductor element surrounded by an insulating member wiring structures on upper and lower surfaces of the semiconductor element and insulating member, and manufacturing method thereof A first semiconductor element is mounted on a base plate, and is in a sealed state by the periphery thereof being covered by an insulation member, and the upper surface thereof being covered by an upper insulation film. An upper wiring layer formed on the upper insu... | 04/06/2010 |
| 7687900 | Semiconductor integrated circuit device and fabrication method for the same The semiconductor integrated circuit device includes: an active element, an interlayer insulting film, first and second metal patterns made of a first metal layer formed right above the active element, first and second buses made of a second metal layer formed right... | 03/30/2010 |
| 7683472 | Power semiconductor modules and method for producing them A power semiconductor module in a pressure contact embodiment and a method for producing such modules, for disposition on a cooling component. Load terminals of the modules are formed as metal molded bodies having at least one contact element, one flat portion, and ... | 03/23/2010 |
| 7679179 | Castellation wafer level packaging of integrated circuit chips Systems and methods for packaging integrated circuit chips in castellation wafer level packaging are provided. The active circuit areas of the chips are coupled to castellation blocks and, depending on the embodiment, input/output pads. The castellation blocks and i... | 03/16/2010 |
| 7675157 | Thermal enhanced package A method of manufacturing an integrated circuit package. The method includes attaching a first surface of a semiconductor die to a thermally and/or electrically conductive substrate, forming a plurality of die connectors on a second surface of the semiconductor die,... | 03/09/2010 |
| 7667315 | Semiconductor device having a frame portion and an opening portion with mountable semiconductor chips therein A semiconductor chip includes a semiconductor substrate having an opening portion and a frame portion defining a periphery of the opening portion. At least one electric element is provided on the frame portion, and has at least one electrode terminal. A first insula... | 02/23/2010 |
| 7663218 | Integrated circuit component with a surface-mount housing A semiconductor component including a surface-mount housing and a method for producing the same are described herein. The semiconductor component includes lead pieces embedded into a plastic housing composition and arranged on an underside of the housing. External c... | 02/16/2010 |
| 7663219 | Semiconductor device and method of manufacturing the same A semiconductor device includes a semiconductor package, a circuit board and an interval maintaining member. The semiconductor package has a body and a lead protruded from the body. The circuit board has a first land electrically connected to the lead. The interval ... | 02/16/2010 |
| 7659611 | Vertical power semiconductor component, semiconductor device and methods for the production thereof A vertical power semiconductor component (1) having a top side (3) and a rear side (4) is provided. The top side (3) has at least one first electrode contact area (8) and at least one control electrode area (9) and the rear ... | 02/09/2010 |
| 7656019 | Semiconductor device and a manufacturing method of the same A semiconductor device is disclosed wherein first wiring lines in a first row extend respectively from first connecting portions toward one side of a semiconductor chip, while second wiring lines extend respectively from second connecting portions toward the side op... | 02/02/2010 |
| 7656020 | Packaging conductive structure for a semiconductor substrate having a metallic layer A packaging conductive structure for a semiconductor substrate and a method for forming the structure are provided. The dielectric layer of the packaging conductive structure partially overlays the metallic layer of the semiconductor substrate and has a receiving sp... | 02/02/2010 |
| 7649250 | Semiconductor package Provided are a semiconductor package and a method for manufacturing the same. The semiconductor package includes: a substrate having a top surface on which a lead is formed and a bottom surface opposite to the top surface; a semiconductor chip attached to the top su... | 01/19/2010 |
| 7638870 | Packaging for high speed integrated circuits An integrated circuit package comprises an integrated circuit die comprising N adjacent pads, where N is an integer greater than three. A substrate comprises a first pair of traces including first and second traces and a second pair of traces including third and fou... | 12/29/2009 |
| 7626255 | Device, system and electric element Provided is a device, an assembly comprising said device, a sub-assembly and an element suitable for use in the assembly. The device comprises a body of an electrically insulating material having a first side and an opposite second side, the body being provided with... | 12/01/2009 |
| 7619306 | Semiconductor device having projecting electrode formed by electrolytic plating, and manufacturing method thereof A semiconductor device includes a semiconductor substrate, and a plurality of wiring lines provided on one side of the semiconductor substrate, each of the wiring lines having a connection pad portion. An overcoat film is provided on the wiring lines and the one sid... | 11/17/2009 |
| 7579683 | Memory interface optimized for stacked configurations A semiconductor die includes a plurality of interconnection pads for connecting with a memory die. The two dies are packaged together in a stacked manner. The plurality of pads are disposed so that the circuit layout of the semiconductor die is invariable with respe... | 08/25/2009 |
| 7554187 | Connecting structure, printed substrate, circuit, circuit package and method of forming connecting structure A connecting structure between a circuit and another electronic component, includes a first electrode and a second electrode, and a dielectric material interposed between the first and second electrodes. ... | 06/30/2009 |
| 7550837 | Semiconductor device and voltage regulator A semiconductor device having a chip size package is disclosed. The chip size package comprises a semiconductor chip having at least a bonding pad, at least a terminal of said chip size package and a reroute trace formed between the bonding pad and the terminal on s... | 06/23/2009 |
| 7545032 | Integrated circuit package system with stiffener An integrated circuit package system is provided including forming a mounting structure having an external interconnect, a paddle, and a tie bar; mounting an integrated circuit die on the paddle; soldering a stiffener structure; having an opening; on the mounting st... | 06/09/2009 |
| 7531894 | Method of electrically connecting a microelectronic component A method of electrically connecting a microelectronic component having a first surface bearing a plurality of contacts. The method including the steps of forming a subassembly by juxtaposing a connection component having a support structure and a plurality of elonga... | 05/12/2009 |
| 7528477 | Castellation wafer level packaging of integrated circuit chips Systems and methods for packaging integrated circuit chips in castellation wafer level packaging are provided. The active circuit areas of the chips are coupled to castellation blocks and, depending on the embodiment, input/output pads. The castellation blocks and i... | 05/05/2009 |
| 7518228 | Hybrid integrated circuit device, and method for fabricating the same, and electronic device A hybrid integrated circuit device having high mount reliability comprises a module substrate which is a ceramic wiring substrate, a plurality of electronic component parts laid out on the main surface of the module substrate, a plurality of electrode terminals laid... | 04/14/2009 |
| 7511369 | BGA-scale stacks comprised of layers containing integrated circuit die and a method for making the same A three dimensional electronic module is disclosed. Conventional TSOP packages are modified to expose internal lead frame interconnects, thinned and stacked on a reroute substrate. The reroute substrate comprises conductive circuitry for the input and output of elec... | 03/31/2009 |
| 7446405 | Wafer level chip scale package (WLCSP) with high reliability against thermal stress A wafer level chip scale package includes a semiconductor chip having a plurality of pads; a lower insulation layer having a high Young's modulus of 1˜5 GPa formed on the semiconductor chip to expose the plurality of pads; a plurality of metal patterns formed on th... | 11/04/2008 |
| 7443033 | Post passivation interconnection schemes on top of the IC chips A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over... | 10/28/2008 |
| 7443010 | Matrix form semiconductor package substrate having an electrode of serpentine shape A matrix form semiconductor package substrate that has an electrode situated in-between a plurality of IC package substrates for providing electrical communication to conductive pads on the substrate is provided. The matrix form semiconductor package substrate inclu... | 10/28/2008 |
| 7443034 | Post passivation interconnection schemes on top of the IC chips A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over... | 10/28/2008 |
| 7443027 | Electronic device having coalesced metal nanoparticles An apparatus composed of: (a) a substrate; and (b) a deposited composition comprising a liquid and a plurality of metal nanoparticles with a covalently bonded stabilizer. ... | 10/28/2008 |
| 7439627 | Post passivation interconnection schemes on top of the IC chips A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over... | 10/21/2008 |
| 7439613 | Substrate based unmolded package A semiconductor die package is disclosed. In one embodiment, the semiconductor die package has a substrate. It includes (i) a leadframe structure including a die attach region with a die attach surface and a lead having a lead surface, and (ii) a molding material. T... | 10/21/2008 |
