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| Number | Title | Issue Date |
| 8188588 | Manufacturing method of substrate for a semiconductor package, manufacturing method of semiconductor package, substrate for a semiconductor package and semiconductor package A manufacturing method of a substrate for a semiconductor package includes a resist layer forming step to form a resist layer on a surface of a conductive substrate; an exposure step to expose the resist layer using a glass mask with a mask pattern including a trans... | 05/29/2012 |
| 8188587 | Semiconductor die package including lead with end portion A semiconductor die package, and methods of making the same. The package includes a leadframe and a clip structure. The clip structure is formed, such that a portion of the clip structure points towards the semiconductor die and is coplanar with the leadframe. The s... | 05/29/2012 |
| 8183682 | Methods of packaging a semiconductor die and package formed by the methods A method of packaging a semiconductor die. The method comprises mounting a semiconductor die to a die attach pad on a carrier and electrically coupling an electrode of the semiconductor die and a contact pad on the carrier with a clip carried by a sacrificial substr... | 05/22/2012 |
| 8183683 | Semiconductor device and fabricating method thereof A semiconductor device is provided. The semiconductor device comprises a semiconductor die having bond pads, each of which consists of a first bond pad made of a material whose ionization tendency is relatively low and a second bond pad made of a material whose ioni... | 05/22/2012 |
| 8178962 | Semiconductor device package and methods of manufacturing the same A semiconductor device package and methods of manufacturing the same are described. In some examples, a semiconductor device includes an IC die including a ring of die pads around a periphery thereof, lands disposed within the ring of die pads, bond terminals couple... | 05/15/2012 |
| RE43380 | Semiconductor device including semiconductor element surrounded by an insulating member and wiring structures on upper and lower surfaces of the semiconductor element and insulating member, and manufacturing method thereof A first semiconductor element is mounted on a base plate, and is in a sealed state by the periphery thereof being covered by an insulation member, and the upper surface thereof being covered by an upper insulation film. An upper wiring layer formed on the upper insu... | 05/15/2012 |
| 8169068 | IO cell with multiple IO ports and related techniques for layout area saving An IO cell with multiple IO ports and related techniques are provided. The IO cell has a plurality of IO ports for transmitting signal of a same IO pin, and each IO port corresponds to a predetermined region for containing an IO pad, wherein at least one of the plur... | 05/01/2012 |
| 8169067 | Low profile ball grid array (BGA) package with exposed die and method of making same Methods and apparatuses for improved thermal, electrical and/or mechanical performance in integrated circuit (IC) packages are described. An IC circuit package comprises a substrate having a central opening. An IC die, resides within the opening in the substrate. Wi... | 05/01/2012 |
| 8143713 | Chip-on-board package Provided is a chip-on-board package. The chip-on-board package may include a board, a grounding pad on a first surface of the board, the grounding pad including a body portion and at least one line portion, and at least two conductive pads on the first surface, the ... | 03/27/2012 |
| 8134230 | Sealed joint structure of device and process using the same A sealed joint structure of device includes a buffer bump layer, conductive joint portions and a sealed joint portion. The buffer bump layer disposed between a device and a substrate includes first parts and a second part surrounding the first parts. Each of the con... | 03/13/2012 |
| 8129835 | Package substrate having semiconductor component embedded therein and fabrication method thereof A package substrate having a semiconductor component embedded therein and a method of fabricating the same are provided, including: providing a semiconductor chip with electrode pads disposed on an active surface thereof; forming a passivation layer on the active su... | 03/06/2012 |
| 8125071 | Package structure utilizing high and low side drivers on separate dice In the specification and drawing a package structure is described and shown with a first die including a high side driver and at least a first bonding pad, a second die including a low side driver, a high withstand voltage device, a controller coupled with the low s... | 02/28/2012 |
| 8125070 | Semiconductor component A semiconductor component has at least one semiconductor chip in which an electrical circuit is integrated. The semiconductor chip is surrounded by an electrically insulating encapsulating compound and has on its surface at least one termination surface for a test s... | 02/28/2012 |
| 8120163 | Non-reciprocal device having grounding arrangement and method of installation thereof A structure of a high frequency non-reciprocal passive device, such as circulator/isolator and method of installation. The structure includes a substantially rigid lip with cutouts for hot leads to go through. The walls of the cutout are situated in close proximity ... | 02/21/2012 |
| 8120161 | Semiconductor module including semiconductor chips coupled to external contact elements A component includes a first semiconductor chip attached to a first carrier and second semiconductor chip attached to a second carrier. The first carrier has a first extension, which forms a first external contact element. The second carrier has a second extension, ... | 02/21/2012 |
| 8120162 | Package with improved connection of a decoupling capacitor A package (216) for electrically connecting an integrated circuit (212) to a printed circuit board (214) includes a mount array (219) and a substrate body (216A). The mount array (219) is electrically connected to the integr... | 02/21/2012 |
| 8115294 | Multichip module with improved system carrier A power semiconductor device has a first chip carrier part (11) and a second chip carrier part (12), the first chip carrier part (11) and the second chip carrier part (12) being spaced apart from one another and being electrically conduct... | 02/14/2012 |
| 8110912 | Semiconductor device A method of manufacturing a semiconductor device includes providing a foil formed of an insulating material, where the foil includes at least one electrically conducting element, providing a chip having contact elements on a first face of the chip, and applying the ... | 02/07/2012 |
| 8106502 | Integrated circuit packaging system with plated pad and method of manufacture thereof A method of manufacture of an integrated circuit packaging system includes: forming an external interconnect; forming a first planar terminal adjacent to the external interconnect and non-planar to a portion the external interconnect; mounting a first integrated cir... | 01/31/2012 |
| 8102042 | Reducing plating stub reflections in a chip package using resistive coupling Improving signal quality in a high-frequency chip package by resistively connecting an open-ended plating stub to ground. One embodiment provides a multi-layer substrate for interfacing a chip with a printed circuit board. A conductive first layer provides a chip mo... | 01/24/2012 |
| 8097941 | Semiconductor device having projecting electrode formed by electrolytic plating, and manufacturing method thereof A semiconductor device includes a semiconductor substrate, and a plurality of wiring lines provided on one side of the semiconductor substrate, each of the wiring lines having a connection pad portion. An overcoat film is provided on the wiring lines and the one sid... | 01/17/2012 |
| 8089145 | Semiconductor device including increased capacity leadframe In accordance with the present invention, there is provided a semiconductor package (e.g., a QFP package) including a uniquely configured leadframe sized and configured to maximize the available number of exposed leads in the semiconductor package. More particularly... | 01/03/2012 |
| 8067830 | Dual or multiple row package A dual or multiple row package (300) is provided which comprises a first plurality of terminals (303, 304, 305) and a second plurality of terminals (306, 307), which first and second plurality of terminals are exposed outside the encapsulation a... | 11/29/2011 |
| 8063479 | Housing for a semiconductor component A housing for a semiconductor component, in which the housing has a plurality of pins which are provided at the edge of the housing at distances, the pins each having a width, a thickness and a length. In order to create a housing for a semiconductor component whose... | 11/22/2011 |
| 8053885 | Wafer level vertical diode package structure and method for making the same A wafer level vertical diode package structure includes a first semiconductor layer, a second semiconductor layer, an insulative unit, a first conductive structure, and a second conductive structure. The second semiconductor layer is connected with one surface of th... | 11/08/2011 |
| 8049323 | Chip holder with wafer level redistribution layer A chip holder formed of silicon, glass, other ceramics or other suitable materials includes a plurality of recesses for retaining semiconductor chips. The bond pads of the semiconductor chip are formed on or over an area of the chip holder that surrounds the semicon... | 11/01/2011 |
| 8044499 | Wiring substrate, manufacturing method thereof, semiconductor device, and manufacturing method thereof A wiring substrate is provided, including an insulating resin layer which is provided on both surfaces of a sheet-like fibrous body and with which the sheet-like fibrous body is impregnated, and a through wiring provided in a region surrounded by the insulating resi... | 10/25/2011 |
| 8039944 | Electrical connection device and assembly method thereof An electrical connection device and assembly method thereof includes a substrate with a plurality of contacting portions arranged on a surface thereof; a chip module having a plurality of terminals inclining in one direction and compressed and contacted with the con... | 10/18/2011 |
| 8039945 | Plastic electronic component package A plastic package for an image sensor or other electronic component which comprises a plastic body, preferably of LCP material, molded around a leadframe and defining a cavity in which the image sensor is to be disposed. A lid assembly is provided having a transpare... | 10/18/2011 |
| 8035212 | Semiconductor chip mounting body, method of manufacturing semiconductor chip mounting body and electronic device According to one embodiment, a semiconductor chip mounting body, with an enhanced shock-resistance at portions of the bonding member corresponding to the corners of a semiconductor chip, is provided. The semiconductor chip mounting body includes a circuit board havi... | 10/11/2011 |
| 8030750 | Semiconductor device packages with electromagnetic interference shielding Described herein are semiconductor device packages with EMI shielding and related methods. In one embodiment, a semiconductor device package includes a circuit substrate, an electronic device, an encapsulant, and a conductive layer. The substrate includes a carrying... | 10/04/2011 |
| 8026589 | Reduced profile stackable semiconductor package In accordance with the present invention, there is provided multiple embodiments of a reduced profile stackable semiconductor package. The semiconductor package comprises a substrate having at least one semiconductor die attached thereto. The semiconductor die is al... | 09/27/2011 |
| 8026590 | Die package and method of manufacturing the same Disclosed herein are a die package and a method of manufacturing the die package. A solder layer is formed on a lower surface of a die. The die is self-aligned and attached to a support plate using surface tension between the solder layer and a metal layer of the su... | 09/27/2011 |
| 8026588 | Method of wire bonding over active area of a semiconductor circuit A method and structure are provided to enable wire bond connections over active and/or passive devices and/or low-k dielectrics, formed on an Integrated Circuit die. A semiconductor substrate having active and/or passive devices is provided, with interconnect metall... | 09/27/2011 |
| 8018043 | Semiconductor package having side walls and method for manufacturing the same A semiconductor package includes a semiconductor chip having an upper surface, side surfaces connected with the upper surface, and bonding pads formed on the upper surface. A first insulation layer pattern is formed to cover the upper surface and the side surfaces o... | 09/13/2011 |
| 8013432 | Package substrate, semiconductor package having the package substrate A package substrate includes an insulating substrate having a mount region including external terminals mounted to the insulating substrate and a clamp region having an opening receiving a molding material therein, the clamp region disposed adjacent to the mount reg... | 09/06/2011 |
| 8004076 | Microelectronic package with carbon nanotubes interconnect and method of making same A method of forming a microelectronic package is provided. The method includes providing a silicon substrate having a plurality of carbon nanotubes disposed on a silicon layer and coupling the silicon substrate to a top surface of a packaging substrate, wherein the ... | 08/23/2011 |
| 7999369 | Power electronic package having two substrates with multiple semiconductor chips and electronic components A power electronic package includes: first and second high thermal conductivity insulating non-planar substrates; and multiple semiconductor chips and electronic components between the substrates. Each substrate includes multiple electrical insulator layers and patt... | 08/16/2011 |
| 7999370 | Semiconductor chip capable of increased number of pads in limited region and semiconductor package using the same A semiconductor package includes a semiconductor chip including a body unit having one or more circuit units. A first bonding pad is disposed in a first face of the body unit and is connected to a circuit unit. A second bonding pad is disposed in the first face of t... | 08/16/2011 |
| 7994628 | Package structure of photoelectronic device and fabricating method thereof A package structure for photoelectronic devices comprises a silicon substrate, a first insulating layer, a reflective layer, a second insulating layer, a first conductive layer, a second conductive layer and a die. The silicon substrate has a first surface and a sec... | 08/09/2011 |
