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| Number | Title | Issue Date |
| 8174017 | Integrating three-dimensional high capacitance density structures Disclosed are three-dimensional dielectric structures on high surface area electrodes and fabrication methods. Exemplary structures comprise a copper foil substrate, trench electrodes or high surface area porous electrode structures formed on the substrate, a insula... | 05/08/2012 |
| 8063404 | Semiconductor memory device A semiconductor memory device positioned on an SOI substrate. A semiconductor memory device includes two transistors with three terminals which serve as a source, a reading drain and a writing drain, respectively. The writing drain is heavily-doped for high writing ... | 11/22/2011 |
| 8022409 | Semiconductor device with omega gate and method for fabricating a semiconductor device A substrate has an active region divided into storage node contact junction regions, channel regions and a bit line contact junction region. Device isolation layers are formed in the substrate isolating the active region from a neighboring active region Recess patte... | 09/20/2011 |
| 7902552 | Semiconductor device having a recess channel structure and method for manufacturing the same A semiconductor device includes a semiconductor substrate having an active region comprising a gate area, a bit line contact area and a storage node contact area. A recess is formed in the gate area and the bit line contact area. A gate is formed over the gate area ... | 03/08/2011 |
| 7800112 | Semiconductor device comprising MIM capacitor A conductive film embedded in a predetermined region on an upper surface of an insulation film and metallic wirings embedded so as to penetrate through the conductive film and protrudes into the insulation film constitute a lower electrode of an MIM capacitor. ... | 09/21/2010 |
| 7800111 | Trench silicon-on-insulator (SOI) DRAM cell The present invention relates to a trench silicon-on-insulator (SOI) dynamic random access memory (DRAM) cell and a method for making the same. A source and a drain are utilized to each connect to one of two semiconductor conductive units on an external side of a ma... | 09/21/2010 |
| 7795620 | Transistor structure and dynamic random access memory structure including the same A dynamic random access memory structure is disclosed, in which, the active area is a donut-type pillar at which a novel vertical transistor is disposed and has a gate filled in the central cavity of the pillar and upper and lower sources/drains located in the upper... | 09/14/2010 |
| 7781773 | Transistor array for semiconductor memory devices and method for fabricating a vertical channel transistor array A transistor array for semiconductor memory devices is provided. A plurality of semiconductor pillars extending outwardly from a bulk section of a semiconductor substrate is arranged in rows and columns. Each pillar forms an active area of a vertical channel access ... | 08/24/2010 |
| 7768014 | Memory device and manufacturing method thereof As for a memory element implemented in a semiconductor device typified by an RFID, it is an object of the present invention to reduce manufacturing steps and to provide a memory element and a memory circuit having the element with reduced cost. It is a feature of th... | 08/03/2010 |
| 7692196 | Memory devices and methods of manufacturing the same The memory device includes a first tunnel insulation layer pattern on a semiconductor substrate, a second tunnel insulation layer pattern having an energy band gap lower than that of the first tunnel insulation layer pattern on the first tunnel insulation layer patt... | 04/06/2010 |
| 7652290 | Standby current erasion circuit of DRAM The present invention discloses a standby current erasion circuit applied in DRAM, which improves prior art word line driving circuit to have the word line voltage outputted in standby mode be equal to the bit line voltage, thereby the short DC standby current betwe... | 01/26/2010 |
| 7592626 | Capacitor and method of manufacturing same A capacitor comprises: a lower electrode formed of a foil made of a polycrystalline metal; an upper conductor layer; and a dielectric layer disposed between the lower electrode and the upper electrode layer. Grain boundaries of the polycrystalline metal appear at th... | 09/22/2009 |
| 7582901 | Semiconductor device comprising metal insulator metal (MIM) capacitor An MIM capacitor using a high-permittivity dielectric film such as tantalum oxide. The MIM capacitor includes an upper electrode, a dielectric film, and a lower electrode. A second dielectric film and the dielectric film are formed between the upper electrode and th... | 09/01/2009 |
| 7521714 | Capacitor and manufacturing method thereof A capacitor capable of being formed in a vertical plane without an additional mask process and/or deposition process and a method of manufacturing the same are provided. The capacitor includes: a first conductive line formed on a substrate; a first interlayer dielec... | 04/21/2009 |
| 7488981 | Memory devices having sharp-tipped phase change layer patterns Phase change Random Access Memory (PRAM) devices include a substrate and a phase change layer pattern on the substrate. The phase change layer pattern includes a sharp tip and at least one wall that extends from the sharp tip in a direction away from the substrate. ... | 02/10/2009 |
| 7432149 | CMOS on SOI substrates with hybrid crystal orientations Methods and structures for CMOS devices with hybrid crystal orientations using double SOI substrates is provided. In accordance with preferred embodiments, a manufacturing sequence includes the steps of forming an SOI silicon epitaxy layer after the step of forming ... | 10/07/2008 |
| 7425724 | Memory device and method of production and method of use of same and semiconductor device and method of production of same A memory device able to be produced without requiring high precision alignment, a method of production of the same, and a method of use of a memory device produced in this way, wherein a peripheral circuit portion (first semiconductor portion) formed by a first mini... | 09/16/2008 |
| 7420261 | Bulk nitride mono-crystal including substrate for epitaxy The invention relates to a substrate for epitaxy, especially for preparation of nitride semiconductor layers. Invention covers a bulk nitride mono-crystal characterized in that it is a mono-crystal of gallium nitride and its cross-section in a plane perpendicular to... | 09/02/2008 |
| 7414278 | Semiconductor device with shallow trench isolation which controls mechanical stresses The semiconductor device comprises a semiconductor substrate 10 with a trench 16a and a trench 16b formed in; a device isolation film 32a buried in the trench 16a and including a liner film including a s... | 08/19/2008 |
| 7411215 | Display device and method of fabricating the same To achieve promotion of stability of operational function of display device and enlargement of design margin in circuit design, in a display device including a pixel portion having a semiconductor element and a plurality of pixels provided with pixel electrodes conn... | 08/12/2008 |
| 7405122 | Methods for fabricating a capacitor A method for forming a capacitor comprises providing a substrate. A bottom electrode material layer is formed on the substrate. A first mask layer is formed on the bottom electrode material layer. A second mask layer is formed on the first mask layer. The second mas... | 07/29/2008 |
| 7390730 | Method of fabricating a body capacitor for SOI memory A semiconductor structure having a body capacitance plate, which is formed with a process that assures that the body capacitance plate is self-aligned to both the source line (SL) diffusion and the bitline diffusion is provided. Thus the amount of overlap between th... | 06/24/2008 |
| 7388248 | Dielectric relaxation memory A capacitor structure having a dielectric layer disposed between two conductive electrodes, wherein the dielectric layer contains at least one charge trap site corresponding to a specific energy state. The energy states may be used to distinguish memory states for t... | 06/17/2008 |
| 7375376 | Semiconductor display device and method of manufacturing the same A semiconductor display device with an interlayer insulating film in which surface levelness is ensured with a limited film formation time, heat treatment for removing moisture does not take long, and moisture in the interlayer insulating film is prevented from esca... | 05/20/2008 |
| 7368752 | DRAM memory cell A DRAM memory cell is provided with a selection transistor, which is arranged horizontally at a semiconductor substrate surface and has a first source/drain electrode, a second source/drain electrode, a channel layer arranged between the first and the second source/... | 05/06/2008 |
| 7365383 | Method of forming an EPROM cell and structure therefor An EPROM cell includes a control gate and a control transistor. A portion of the control transistor is formed as a portion of the control gate. ... | 04/29/2008 |
| 7361933 | Semiconductor device A semiconductor device includes a first trench capacitor formed in a first trench, a second trench capacitor formed in a second trench, a first gate electrode disposed above a first active area, a second gate electrode disposed above a second active area, a first im... | 04/22/2008 |
| 7355203 | Use of gate electrode workfunction to improve DRAM refresh This invention relates to a method and resulting structure, wherein a DRAM may be fabricated by using silicon midgap materials for transistor gate electrodes, thereby improving refresh characteristics of access transistors. The threshold voltage may be set with redu... | 04/08/2008 |
| 7355231 | Memory circuitry with oxygen diffusion barrier layer received over a well base A method of forming memory circuitry having a memory array having a plurality of memory capacitors and having peripheral memory circuitry operatively configured to write to and read from the memory array, includes forming a dielectric well forming layer over a semic... | 04/08/2008 |
| 7348598 | Thin film transistor and liquid crystal display device using the same A TFT, in which source and drain electrodes having concentric circular shapes are formed, reduces an OFF current caused by a leakage current and optimizes an ON current and a stray capacitance between gate and source electrodes. The TFT includes a gate electrode for... | 03/25/2008 |
| 7342272 | Flash memory with recessed floating gate A flash memory device where the floating gate of the flash memory is defined by a recessed access device. The use of a recessed access device results in a longer channel length with less loss of device density. The floating gate can also be elevated above the substr... | 03/11/2008 |
| 7340175 | Non-uniform optical waveband aggregator and deaggregator and hierarchical hybrid optical cross-connect system Hierarchical hybrid optical networking is based on balancing cost and performance of optical networks by providing transparent (optical) switching of subsets of wavelengths in addition to opaque (electrical) switching of individual light paths. Effective use of wave... | 03/04/2008 |
| 7339191 | Capacitors having doped aluminum oxide dielectrics Doped aluminum oxide layers having a porous aluminum oxide layer and methods of their fabrication. The porous aluminum oxide layer may be formed by evaporation physical vapor deposition techniques to facilitate formation of a high-purity aluminum oxide layer. A dopa... | 03/04/2008 |
| 7335934 | Integrated circuit device, and method of fabricating same There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to integrated circuit device including SOI logic transistors and SOI memory transistors, and method for fabricating such a device. In one embodiment, int... | 02/26/2008 |
| 7332418 | High-density single transistor vertical memory gain cell A memory cell which is formed on a substrate of a first conductivity type. A pillar of the first conductivity type extends vertically upward from the substrate. A source region of a second conductivity type is formed in the substrate extending adjacent to and away f... | 02/19/2008 |
| 7326993 | Nonvolatile semiconductor memory and method for fabricating the same A nonvolatile semiconductor memory includes a first semiconductor layer; second semiconductor regions formed on the first semiconductor layer having device isolating regions extended in a column direction; a first interlayer insulator film formed above the first sem... | 02/05/2008 |
| 7326985 | Method for fabricating metallic bit-line contacts A memory cell and method of forming the same is provided. To make contact between a bit line and a select transistor of a dynamic memory unit on a semiconductor wafer, a contact hole is filled with a metal or a metal alloy. A liner layer may be introduced between th... | 02/05/2008 |
| 7323736 | Method to form both high and low-k materials over the same dielectric region, and their application in mixed mode circuits A new method of provided for forming in one plane layers of semiconductor material having both high and low dielectric constants. Layers, having selected and preferably non-identical parameters of dielectric constants, are successively deposited interspersed with la... | 01/29/2008 |
| 7324367 | Memory cell and method for forming the same A semiconductor memory cell structure having 4 F2 dimensions and method for forming the same. The memory cell is formed on a surface of a substrate and includes an active region formed in the substrate, a semiconductor post formed on the surface of the su... | 01/29/2008 |
| 7321145 | Method and apparatus for operating nonvolatile memory cells with modified band structure A nonvolatile memory cell with a charge storage structure is read by measuring current (such as band-to-band current) between the substrate region of the memory cell and at least one of the current carrying nodes of the memory cell. To enhance the operation of the n... | 01/22/2008 |
