Famous Patents
Pong, the Atari creation that launched the computer game craze, came with these instructions: "Avoid missing ball for high score."
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8148728 | Method for fabrication of a semiconductor device and structure A method for fabrication of 3D semiconductor devices utilizing a layer transfer and steps for forming transistors on top of a pre-fabricated semiconductor device comprising transistors formed on crystallized semiconductor base layer and metal layer for the transisto... | 04/03/2012 |
| 8030655 | Thin film transistor, display device having thin film transistor A thin film transistor with excellent electric characteristics, a display device having the thin film transistor, and a method for manufacturing the thin film transistor and the display device in a high yield are provided. In the thin film transistor, a gate electro... | 10/04/2011 |
| 8026521 | Semiconductor device and structure A device comprising semiconductor memories, the device comprising: a first layer and a second layer of layer-transferred mono-crystallized silicon, wherein the first layer comprises a first plurality of horizontally-oriented transistors; wherein the second layer com... | 09/27/2011 |
| 7989811 | Manufacturing method of semiconductor device A manufacturing method of a highly reliable semiconductor with a waterproof property. The method includes the steps of: sequentially forming a peeling layer, an inorganic insulating layer, and an element formation layer including an organic compound layer, over a su... | 08/02/2011 |
| 7982221 | Semiconductor memory device having three dimensional structure A semiconductor device and method for arranging and manufacturing the same are disclosed. The semiconductor device includes a plurality of inverters including at least one first pull-up transistor and first pull-down transistor and inverting and outputting an input ... | 07/19/2011 |
| 7973314 | Semiconductor device and method of manufacturing the same A semiconductor device has a first semiconductor layer including a first circuit, a second semiconductor layer disposed on the first semiconductor layer and having a second circuit, and a via extending through portions of the first and second semiconductor layers an... | 07/05/2011 |
| 7834358 | Semiconductor LSI circuit and a method for fabricating the semiconductor LSI circuit Basic logic gates are formed in a small area, and a highly integrated and microscopic structure is provided. In an nMOSFET and a pMOSFET, gate electrodes are formed facing each other and sandwiching a semiconductor region via gate insulting layers. Respective drain ... | 11/16/2010 |
| 7795619 | Semiconductor device A method for manufacturing a semiconductor device, including the steps of: forming a shielding film 38 on a first insulating film 37; sequentially forming a second insulating film 39 and an amorphous semiconductor film 40 on the shielding... | 09/14/2010 |
| 7741644 | Semiconductor device having stacked transistors A semiconductor device includes a first semiconductor layer, a first interlayer insulation layer, a second semiconductor layer, and a gate pattern. The first interlayer insulation layer covers the first semiconductor layer. The second semiconductor layer is formed o... | 06/22/2010 |
| 7741645 | Three-dimensional integrated heterogeneous semiconductor structure A first set of semiconductor devices is formed on a first semiconductor substrate comprising a first semiconductor material having a first melting point. A first via-level dielectric layer containing first contact vias is formed on the first semiconductor substrate.... | 06/22/2010 |
| 7619251 | Laser crystallization method suppressing propagation of cracks forming a display device A method of irradiating at least a part of a semiconductor film on the substrate with a CW or pseudo-CW laser beam so as to grow crystals laterally. A region over the semiconductor film having Si as a chief component is provided with a pixel region, a gate line driv... | 11/17/2009 |
| 7592625 | Semiconductor transistor with multi-level transistor structure and method of fabricating the same Example embodiments relate to a semiconductor device and a method of fabricating the same. The device may include a semiconductor substrate including a peripheral region and a cell array region, wherein the substrate in the cell array region may be recessed lower th... | 09/22/2009 |
| 7579623 | Stacked transistors and process A method of horizontally stacking transistors on a common semiconductor substrate is initiated by providing a single crystal, generally silicon, semiconductor substrate. A plurality of transistors are formed on the single crystal semiconductor substrate and encapsul... | 08/25/2009 |
| 7547917 | Inverted multilayer semiconductor device assembly An apparatus and method for an inverted multilayer silicon over insulator (SOI) device is provided. In the multilayer SOI device, the crystal orientation of at least one active region of a device may be different than the active region of at least another device. Wh... | 06/16/2009 |
| 7538351 | Method for forming an SOI structure with improved carrier mobility and ESD protection A semiconductor device and method for forming the same including improved electrostatic discharge protection for advanced semiconductor devices, the semiconductor device including providing semiconductor substrate having a pre-selected surface orientation and crysta... | 05/26/2009 |
| 7525121 | Coplanar silicon-on-insulator (SOI) regions of different crystal orientations and methods of making the same In a first aspect, a first method is provided for semiconductor device manufacturing. The first method includes the steps of (1) providing a substrate; and (2) forming a first silicon-on-insulator (SOI) region having a first crystal orientation, a second SOI region ... | 04/28/2009 |
| 7521713 | Semiconductor device having electrostatic discharge element A semiconductor device includes a laminated substrate; a removal portion; a cavity; a first semiconductor element; and a second semiconductor element. In the laminated substrate, a bulk layer, an insulating layer, and a semiconductor layer are laminated in this orde... | 04/21/2009 |
| 7491973 | Semiconductor LSI circuit having a NAND logic gate with a highly integrated and microscopic structure Basic logic gates are formed in a small area, and a highly integrated and microscopic structure is provided. In an nMOSFET and a pMOSFET, gate electrodes are formed facing each other and sandwiching a semiconductor region via gate insulting layers. Respective drain ... | 02/17/2009 |
| 7439542 | Hybrid orientation CMOS with partial insulation process The present invention provides a method of integrated semiconductor devices such that different types of devices are formed upon a specific crystallographic orientation of a hybrid substrate. In accordance with the present invention, junction capacitance of one of t... | 10/21/2008 |
| 7411215 | Display device and method of fabricating the same To achieve promotion of stability of operational function of display device and enlargement of design margin in circuit design, in a display device including a pixel portion having a semiconductor element and a plurality of pixels provided with pixel electrodes conn... | 08/12/2008 |
| 7410595 | Refrigerant compositions Refrigerant composition are disclosed which comprises: (a) pentafluoroethane, trifluoromethoxydifluoromethane or hexafluorocyclopropane, or a mixture of two or more thereof, in an amount of at least 75% based on the weight of the composition, (b) 1,1,1... | 08/12/2008 |
| 7408193 | Semiconductor device and manufacturing method thereof A semiconductor device packaged in three dimensions comprises a first thin film device, a second thin film device, and a third thin film device, each of the first, second, and third thin film devices comprising a first insulating film, a first electrode formed over ... | 08/05/2008 |
| 7402496 | Complementary metal-oxide-semiconductor device and fabricating method thereof A complementary metal-oxide-semiconductor (CMOS) device includes a substrate with a first active region and a second active region; a first gate structure and a second gate structure, respectively disposed on the first active region and the second active region; a f... | 07/22/2008 |
| 7388248 | Dielectric relaxation memory A capacitor structure having a dielectric layer disposed between two conductive electrodes, wherein the dielectric layer contains at least one charge trap site corresponding to a specific energy state. The energy states may be used to distinguish memory states for t... | 06/17/2008 |
| 7381989 | Semiconductor device including upper and lower transistors and interconnection between upper and lower transistors A stacked semiconductor device comprises a lower transistor formed on a semiconductor substrate, a lower interlevel insulation film formed on the semiconductor substrate over the lower transistor, an upper transistor formed on the lower interlayer insulation film ov... | 06/03/2008 |
| 7372720 | Methods and apparatus for decreasing soft errors and cell leakage in integrated circuit structures Methods and apparatus are provided for decreasing soft errors and cell leakage in integrated circuit structures. The structures of the invention preferably include memory cells that utilize thin-film transistors (“TFTs”) for the pull-up and pull-down transistors... | 05/13/2008 |
| 7371619 | Semiconductor device and method of manufacturing the same In order to obtain a thin-film transistor having high characteristics using a metal element for accelerating the crystallization of silicon, a nickel element is selectively added to the surface of an amorphous silicon film (103) in regions (101) and ( | 05/13/2008 |
| 7372101 | Sub-lithographics opening for back contact or back gate A low resistance buried back contact for SOI devices. A trench is etched in an insulating layer at minimum lithographic dimension, and sidewalls are deposited in the trench to decrease its width to sublithographic dimension. Conducting material is deposited in the t... | 05/13/2008 |
| 7368337 | Semiconductor device and manufacturing method thereof A semiconductor device and method of manufacturing the same are disclosed. An example semiconductor device includes a semiconductor substrate having a first well, a first source electrode, a drain electrode, and a first gate insulation layer formed on the semiconduc... | 05/06/2008 |
| 7368788 | SRAM cells having inverters and access transistors therein with vertical fin-shaped active regions Complementary metal oxide semiconductor (CMOS) static random access memory (SRAM) cells include at least a first inverter formed in a fin-shaped pattern of stacked semiconductor regions of opposite conductivity type. In some of these embodiments, the first inverter ... | 05/06/2008 |
| 7355202 | Thin-film transistor A gate-insulated thin film transistor is disclosed. One improvement is that the thin film transistor is formed on a substrate through a blocking layer in between so that it is possible to prevent the transistor from being contaminated with impurities such as alkali ... | 04/08/2008 |
| 7348598 | Thin film transistor and liquid crystal display device using the same A TFT, in which source and drain electrodes having concentric circular shapes are formed, reduces an OFF current caused by a leakage current and optimizes an ON current and a stray capacitance between gate and source electrodes. The TFT includes a gate electrode for... | 03/25/2008 |
| 7348658 | Multilayer silicon over insulator device An apparatus and method for a multilayer silicon over insulator (SOI) device is provided. In the multilayer SOI device, the crystal orientation of at least one active region of a device is different than the active region of at least another device. Where the multil... | 03/25/2008 |
| 7348226 | Method of forming lattice-matched structure on silicon and structure formed thereby A method (and resultant structure) of forming a semiconductor structure, includes processing an oxide to have a crystalline arrangement, and depositing an amorphous semiconductor layer on the oxide by one of evaporation and chemical vapor deposition (CVD). ... | 03/25/2008 |
| 7342273 | Applying epitaxial silicon in disposable spacer flow A process for forming active transistors for a semiconductor memory device by the steps of: forming transistor gates having generally vertical sidewalls in a memory array section and in periphery section; implanting a first type of conductive dopants into exposed si... | 03/11/2008 |
| 7339812 | Stacked 1T-memory cell structure This invention relates to memory technology and new variations on memory array architecture to incorporate certain advantages from both cross-point and 1T-1Cell architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1Cell architecture and the h... | 03/04/2008 |
| 7339213 | Semiconductor device having a triple gate transistor and method for manufacturing the same In a semiconductor capable of reducing NBTI and a method for manufacturing the same, a multi-gate transistor includes an active region, gate dielectric, channels in the active region, and gate electrodes, and is formed on a semiconductor wafer. The active region has... | 03/04/2008 |
| 7332385 | Method of manufacturing a semiconductor device that includes gettering regions A catalytic element is added to an amorphous semiconductor film and heat treatment is conducted therefor to produce a crystalline semiconductor film with good quality, a TFT (semiconductor device) with a satisfactory characteristic is realized using the crystalline ... | 02/19/2008 |
| 7329914 | Charge trapping memory device with two separated non-conductive charge trapping inserts and method for making the same A charge trapping memory device with two separated non-conductive charge trapping inserts is disclosed. The charge trapping memory device has a silicon substrate with two junctions. A gate oxide (GOX) is formed on top of the silicon substrate and between the two jun... | 02/12/2008 |
| 7329916 | DRAM cell arrangement with vertical MOS transistors The invention is related to a DRAM cell arrangement with vertical MOS transistors. Channel regions arranged along one of the columns of a memory cell matrix are parts of a rib which is surrounded by a gate dielectric layer. Gate electrodes of the MOS transistors bel... | 02/12/2008 |
