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| Number | Title | Issue Date |
| 7973393 | Stacked micro optocouplers and methods of making the same Disclosed are packages for optocouplers and methods of making the same. An exemplary optocoupler comprises a substrate having a first surface and a second surface, a plurality of optoelectronic dice for one or more optocouplers disposed on the substrate's first surf... | 07/05/2011 |
| 7884450 | Growth of boron nanostructures with controlled diameter A process for growth of boron-based nanostructures, such as nanotubes and nanowires, with a controlled diameter and with controlled chemical (such as composition, doping) as well as physical (such as electrical and superconducting) properties is described. The boron... | 02/08/2011 |
| 7531892 | Superconducting boron nanostructures A process for growth of boron-based nanostructures, such as nanotubes and nanowires, with a controlled diameter and with controlled chemical (such as composition, doping) as well as physical (such as electrical and superconducting) properties is described. The boron... | 05/12/2009 |
| 7440449 | High speed switching module comprised of stacked layers incorporating t-connect structures A compact multi-stage switching network (100), and a router (510) incorporating such multi-stage switching network, adapted for simultaneously routing a plurality of data packets from a first plurality of input ports (110) to selected ones of a ... | 10/21/2008 |
| 7341875 | Semiconductor memory device with a capacitor formed therein and a method for forming the same To integrate a capacitor device (40) into the region of a semiconductor memory device with a particularly small number of process steps, a lower electrode device (43) and an upper electrode device (44) of the capacitor device (40) are pro... | 03/11/2008 |
| 7327022 | Assembly, contact and coupling interconnection for optoelectronics A novel micro optical system as a platform technology for electrical and optical interconnections, thermal and mechanical assembly and integration of electronic, optoelectronic, passive and active components. This platform provides optical coupling and chip-to-chip ... | 02/05/2008 |
| 7282445 | Multiple seed layers for interconnects One embodiment of the present invention is a method for depositing two or more seed layers over a substrate, the substrate includes a patterned insulating layer which comprises at least one opening surrounded by a field, the at least one opening and the field being ... | 10/16/2007 |
| 7268052 | Method for reducing soft error rates of memory cells In one embodiment, a method of fabricating a transistor for a memory cell includes the steps of performing a counter doping implant before or after a source/drain implant. The counter doping implant may comprise one or more implant steps that move a metallurgical ju... | 09/11/2007 |
| 7199052 | Seed layers for metallic interconnects One embodiment of the present invention is a method for making copper or a copper alloy interconnects, which method includes: (a) forming a patterned insulating layer over a substrate, the patterned insulating layer including at least one opening and a field surroun... | 04/03/2007 |
| 7105434 | Advanced seed layery for metallic interconnects One embodiment of the present invention is a method for making metallic interconnects, which method is utilized at a stage of processing a substrate having a patterned insulating layer which includes at least one opening and a field surrounding the at least one open... | 09/12/2006 |
| 7095042 | Electrode structure, semiconductor light-emitting device having the same and method of manufacturing the same A semiconductor light emitting device including a p-type electrode structure and having a low contact resistance and high reflectance is provided. The semiconductor light emitting device includes a transparent substrate, an electron injection layer having first and ... | 08/22/2006 |
| 7067839 | Tuning circuit with distributed tunnel junction elements and superconductor integrated circuit comprising the tuning circuit It is an object to provide a tuning circuit which has large fractional frequency band width, for example frequency band of the return loss of less than −10 dB. The tuning circuit is composed of a superconductor microstrip lines, a superconductor distributed tunnel... | 06/27/2006 |
| 7060508 | Self-aligned junction passivation for superconductor integrated circuit A superconductor integrated circuit (1) includes an anodization ring (35) disposed around a perimeter of a tunnel junction region (27) for preventing a short-circuit between an outside contact (41) and the base electrode layer (18)... | 06/13/2006 |
| 7042004 | Method of forming quantum-mechanical memory and computational devices and devices obtained thereof The present invention discloses a quantum system comprising computational elements, consisting of an insulated ring of superconductive material, and semi-closed rings, which are used as an interface or input/output facility between the quantum bit and the external w... | 05/09/2006 |
| 7034641 | Substrate structure for photonic assemblies and the like having a low-thermal-conductivity dielectric layer on a high-thermal-conductivity substrate body A substrate structure useful for photonics modules comprises a high-thermal-conductivity (e.g., greater than 20 W/m°K) substrate body with a low-thermal-conductivity (e.g., less than 5 W/m°K) dielectric layer overlying at least a portion of the substrate body. Pat... | 04/25/2006 |
| 6993255 | Method and apparatus for providing adaptive illumination An illumination system (20, 72, 110, 142) for illuminating a scene comprising: an illuminator (24, 74, 116) having a plurality of substantially contiguous independently controllable light (26, 76) providing regions each of which provides light t... | 01/31/2006 |
| 6967393 | Semiconductor differential interconnect An interconnect is described including a semiconductor substrate having opposing surfaces, including first and second insulated conductors for transmitting signals. A third conductor substantially surrounds and is electrically insulated from the first and second ins... | 11/22/2005 |
| 6956281 | Semiconductor device for reducing photovolatic current A semiconductor device that has a common border between P and N wells is susceptible to photovoltaic current that is believed to be primarily generated from photons that strike this common border. Photons that strike the border are believed to create electron/hole p... | 10/18/2005 |
| 6924226 | Methods for making multiple seed layers for metallic interconnects One embodiment of the present invention is a method for making metallic interconnects, which method is utilized at a stage of processing a substrate having a patterned insulating layer which includes at least one opening and a field surrounding the at least one open... | 08/02/2005 |
| 6903016 | Combined conformal/non-conformal seed layers for metallic interconnects One embodiment of the present invention in a method for making copper interconnects, which method includes: (a) forming a patterned insulating layer on a substrate, the patterned insulating layer including at least one opening and a field surrounding the at least on... | 06/07/2005 |
| 6897548 | Semiconductor differential interconnect An interconnect is described including a semiconductor substrate having opposing surfaces, including first and second insulated conductors for transmitting signals. A third conductor substantially surrounds and is electrically insulated from the first and second ins... | 05/24/2005 |
| 6873055 | Integrated circuit arrangement with field-shaping electrical conductor An integrated circuit arrangement includes at least one electrical conductor that, when a current flows through it, produces a magnetic field that acts on at least a further part of the circuit configuration, wherein seen in cross-section, the electrical conductor h... | 03/29/2005 |
| 6838749 | Structures for increasing the critical temperature of superconductors A method for increasing the critical temperature, Tc, of a high critical temperature superconducting (HTS) film (104) grown on a substrate (102) and a superconducting structure (100) made using the method. The HTS film has an a-b plan... | 01/04/2005 |
| 6829237 | High speed multi-stage switching network formed from stacked switching layers A compact multi-stage switching network (100), and a router (510) incorporating such multi-stage switching network, adapted for simultaneously routing a plurality of data packets from a first plurality of input ports (110) to selected ones of a ... | 12/07/2004 |
| 6787798 | Method and system for storing information using nano-pinned dipole magnetic vortices in superconducting materials A method includes providing a superconducting material having pinning sites that can pin magnetic vortices within the superconducting material. The method also includes pinning one or more magnetic vortices at one or more of the pinning sites. An information storage... | 09/07/2004 |
| 6777808 | Capacitor for signal propagation across ground plane boundaries in superconductor integrated circuits The self inductance associated with a capacitance A52 in a superconductor integrated circuit (FIG. 1) is reduced by adding a layer of superconductor metal (A54) overlying the capacitor, effectively producing a negative inductance to counteract t... | 08/17/2004 |
| 6740959 | EMI shielding for semiconductor chip carriers Electronic packages incorporating EMI shielding, and particularly semiconductor devices which incorporate semiconductor chip-carrier structures having grounded bands embedded therein which are adapted to reduce outgoing and incident EMI emissions for high-speed swit... | 05/25/2004 |
| 6642608 | MoNx resistor for superconductor integrated circuit A superconductor integrated circuit (10) includes a silicon substrate (12) a niobium ground layer (14), an anodized niobium first ground insulator layer (16), a second ground insulator layer (22), a molybdenum nitrogen (MoNx) resistor (18) prov... | 11/04/2003 |
| 6563185 | High speed electron tunneling device and applications A detector for detecting electromagnetic radiation incident thereon over a desired range of frequencies exhibits a given responsivity and includes an output and first and second non-insulating layers, which layers are spaced apart such that a given voltag... | 05/13/2003 |
| 6552415 | Electrically stabilized thin-film high-temperature superconductor and method for the production thereof An electrically stabilized thin-film high-temperature superconductor includes a superconductive layer (32) applied over a flat metallic substrate (31) and connected to the metallic substrate (31) so that electrical contact between the superconductive laye... | 04/22/2003 |
| 6486533 | Metallization structures for microelectronic applications and process for forming the structures A metallized structure for use in a microelectronic circuit is set forth. The metallized structure comprises a dielectric layer, an ultra-thin film bonding layer disposed exterior to the dielectric layer, and a low-Me concentration, copper-Me alloy layer ... | 11/26/2002 |
| 6377440 | Dielectric varactors with offset two-layer electrodes A varactor comprising a substrate, a first conductor positioned on a surface of the substrate, a second conductor positioned on the surface of the substrate forming a gap between the first and second conductors, a tunable dielectric material positioned on... | 04/23/2002 |
| 6331911 | Large aperture optical image shutter An optical image shutter is provided having a multiplicity of thin layers of alternating narrow and wide gap semiconductor material stacked to form an MQW structure and electrodes located on at least two semiconductor surfaces of the image shutter, wherei... | 12/18/2001 |
| 6323426 | Mounting structure for semiconductor device A mounting structure for a high temperature superconductor device, such as a filter, housed in a closed vacuum chamber and operated at a low temperature. The filter has dielectric substrate having: first and second surfaces; a circuit portion made of a su... | 11/27/2001 |
| 6157044 | Tunnel junction type josephson device A tunnel junction type Josephson device includes a pair of superconductor layers formed of a compound oxide superconductor material and an insulator layer formed between the pair of superconductor layers. The insulator layer is formed of a compound oxide ... | 12/05/2000 |
| 6121630 | Superconducting thin film and a method for preparing the same A high-temperature superconducting thin film of compound oxide selected from the group consisting of: Y1 Ba2 Cu3 O7-x, Ho1 Ba2 Cu3 O7-x, Lu1 Ba2 Cu | 09/19/2000 |
| 6097080 | Semiconductor device having magnetic shield layer circumscribing the device It is the object to minimize a magnetic influence, on the outside, of a semiconductor chip which is formed on a substrate includes inductor conductors. A semiconductor chip 2 including inductor conductors is mounted on a substrate 1 and a plurality of thr... | 08/01/2000 |
| 6088604 | Superconductor-normal conductor junction device A superconductor-normal conductor junction device comprises first and second regions (1, 3) of normal material forming first and second junctions with a superconducting material (2), the Fermi level of the first region of normal material being so arranged... | 07/11/2000 |
| 6087711 | Integrated circuit metallization with superconductor BEOL wiring The present invention discloses an integrated circuit that is wired with a high-temperature superconductive material that is superconductive at temperatures of about 70° K and above, and methods of making the integrated circuit. The front-end manufacture... | 07/11/2000 |
| 6051440 | Method of fabricating a low-inductance in-line resistor for superconductor integrated circuits A method of fabricating a low-inductance, in-line resistor includes the steps of: depositing a superconductive layer 12 on a base layer 14; patterning an interconnect region 16 on the superconductive layer 12; and converting the interconnect region 16 of ... | 04/18/2000 |
