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| Number | Title | Issue Date |
| 7875961 | Semiconductor substrate of GaAs and semiconductor device A semiconductor substrate, of GaAs with a semiconductor layer sequence applied on top of the substrate. The semiconductor layer sequence comprises a plurality of semiconductor layers of Al1-yGayAs1-xPx with 0≦x≦1 and 0... | 01/25/2011 |
| 7838970 | Semiconductor component with high concentration doped zone embedded in emitter region A semiconductor component has a first and a second contact-making region, and a semiconductor volume arranged between the first and the second contact-making region. Within the semiconductor volume, it is possible to generate a current flow that runs from the first ... | 11/23/2010 |
| 7432538 | Field-effect transistor A field-effect transistor includes a channel layer having a channel and a carrier supply layer, disposed on the channel layer, containing a semiconductor represented by the formula AlxGa1-xN, wherein x is greater than 0.04 and less than 0.45. T... | 10/07/2008 |
| 7354838 | Technique for forming a contact insulation layer with enhanced stress transfer efficiency By removing an outer spacer, used for the formation of highly complex lateral dopant profiles, prior to the formation of metal silicide, a high degree of process compatibility with conventional processes is obtained, while at the same time a contact liner layer may ... | 04/08/2008 |
| 7304350 | Threshold voltage control layer in a semiconductor device A semiconductor device has a well region having a first conductivity type and formed in an upper portion of a semiconductor substrate, a gate insulating film and a gate electrode formed successively on the well region of the semiconductor substrate, a threshold volt... | 12/04/2007 |
| 7268079 | Method for fabricating a semiconductor having a field zone A method for fabricating a semiconductor and at least one second semiconductor zone of a semiconductor component having a semiconductor body having a first semiconductor zone. At least one field zone arranged in an edge region of the semiconductor body is reduced in... | 09/11/2007 |
| 7268040 | Method of manufacturing a select transistor in a NAND flash memory Disclosed herein is a method of manufacturing a flash memory device. According to the present invention, a method of manufacturing a NAND flash memory device having a memory cell and a select transistor, wherein a graph showing the relation between the length of a g... | 09/11/2007 |
| 7262467 | Over charge protection device An over-voltage protection device includes a substrate including an upper surface and a lower surface; a first electrode provided on the upper surface of the substrate; a second electrode provided on the lower surface on the substrate; a first conductive layer overl... | 08/28/2007 |
| 7199447 | Angled implant to improve high current operation of bipolar transistors Method and apparatus for improving the high current operation of bipolar transistors while minimizing adverse affects on high frequency response are disclosed. A local implant to increase the doping of the collector at the collector to base interface is achieved by ... | 04/03/2007 |
| 7161220 | High speed photodiode with a barrier layer for blocking or eliminating slow photonic carriers and method for forming same A structure (and method for forming the structure) includes a photodetector, a substrate formed under the photodetector, and a barrier layer formed over the substrate. The buried barrier layer preferably includes a single or dual p-n junction, or a bubble layer for ... | 01/09/2007 |
| 7091579 | Power semiconductor rectifier having broad buffer structure and method of manufacturing thereof Impurity concentration (Nd(X)) in an n-drift layer in a diode is at a maximum at a position at a distance Xp from an anode electrode in a direction from the anode electrode to a cathode electrode, and gradually decreases from the position toward each of t... | 08/15/2006 |
| 6974983 | Isolated FinFET P-channel/N-channel transistor pair A semiconductor device includes an N-channel device and a P-channel device. The N-channel device includes a first source region, a first drain region, a first fin structure, and a gate. The P-channel device includes a second source region, a second drain region, a s... | 12/13/2005 |
| 6972466 | Bipolar transistors with low base resistance for CMOS integrated circuits Complementary metal-oxide-semiconductor (CMOS) integrated circuits with bipolar transistors and methods for fabrication are provided. A bipolar transistor may have a lightly-doped base region. To reduce the resistance associated with making electrical contact to the... | 12/06/2005 |
| 6963126 | Semiconductor device with under-fill material below a surface of a semiconductor chip AS conductive patterns 11A to 11D are formed burying in a insulating resin 10 and a conductive foil 20 is formed being half-etched, thickness of the device is made thin. As an electrode for radiation 11D is provided, a semiconducto... | 11/08/2005 |
| 6960782 | Electronic devices with fullerene layers Described is an electronic device comprising a junction formed between a first fullerene layer having a first doping concentration and a second fullerene layer having a second doping concentration different from the first doping concentration. The first doping conce... | 11/01/2005 |
| 6911715 | Bipolar transistors and methods of manufacturing the same A bipolar transistor in which the occurrence of Kirk effect is suppressed when a high current is injected into the bipolar transistor and a method of fabricating the bipolar transistor are described. The bipolar transistor includes a first collector region of a firs... | 06/28/2005 |
| 6888226 | Semiconductor structure and method for improving its ability to withstand electrostatic discharge (ESD) and overloads A semiconductor structure includes a base layer of a first conductivity type, a first layer of the first conductivity type arranged on the base layer and having a dopant concentration that is lower than a dopant concentration of the base layer, and a second layer of... | 05/03/2005 |
| 6777814 | Semiconductor device A semiconductor device includes a semiconductor chip, and a circuit substrate disposed such that the circuit substrate faces the semiconductor chip and is electrically connected to the semiconductor chip through a connection conductor. A pad electrode and a terminal... | 08/17/2004 |
| 6750532 | CMOS semiconductor device and method of manufacturing the same In a CMOS semiconductor device having a substrate, a gate insulating layer formed on the substrate, at least one first polysilicon gate formed over the substrate in at least one PMOS transistor region, and at least one second polysilicon gate formed over the substra... | 06/15/2004 |
| 6674152 | Bipolar diode A bipolar p-i-n diode has a first (1) and second (5) region of opposite conductivity type and an intermediate drift region (3) between the first and second regions. Trenched field relief regions (14) are arranged to deplete the intermediate drift region (... | 01/06/2004 |
| 6647542 | Efficient fabrication process for dual well type structures An efficient method for fabricating dual well type structures uses the same number of masks used in single well type structure fabrication. In a preferred embodiment, the current invention allows low voltage and high voltage n-channel transistors and low ... | 11/11/2003 |
| 6642558 | Method and apparatus of terminating a high voltage solid state device Termination of a high voltage device is achieved by a plurality of discrete deposits of charge that are deposited in varying volumes and/or spacing laterally along a termination region. The manner in which the volumes and/or spacing varies also varies bet... | 11/04/2003 |
| 6580141 | Trench schottky rectifier A Schottky rectifier is provided. The Schottky rectifier comprises: (a) a semiconductor region having first and second opposing faces, with the semiconductor region comprising a cathode region of first conductivity type adjacent the first face and a drift... | 06/17/2003 |
| 6479356 | Method of manufacturing a semiconductive device with an enhanced junction breakdown strength A gate insulating film and gate electrodes are formed on a substrate containing N-type impurities such as P or As. Under the gate insulating film is a gate region on both sides of which are a first and a second source drain region. The gate region is furn... | 11/12/2002 |
| 6351024 | Power semiconductor diode A semiconductor body including a first surface, a second surface, and a base doping for electrical conductivity. A first doped region is on the first surface and a second doped is on the second surface. The two doped regions are doped with opposites signs... | 02/26/2002 |
| 6180989 | Selectively doped electrostatic discharge layer for an integrated circuit sensor A structure and method for creating an integrated circuit passivation structure comprising, a circuit, a dielectric, and metal plates over which an insulating layer is disposed that electrically isolates the circuit, and a discharge layer that is deposite... | 01/30/2001 |
| 6172420 | Silicon delta-doped gallium arsenide/indium arsenide heterojunction OHMIC contact An ohmic contact including a gallium arsenide substrate having an epitaxially grown crystalline layer of indium arsenide on the substrate. The crystalline material and the substrate define an interface, layers are n-doped with silicon close to the interfa... | 01/09/2001 |
| 6172399 | Formation of ultra-shallow semiconductor junction using microwave annealing The present invention is a method of utilizing microwave energy for annealing of ion implanted wafers. By controlling the time, power density and temperature regime, it is possible to substantially fully anneal the wafer while limiting (and substantially ... | 01/09/2001 |
| 6081007 | Semiconductor device comprising MIS transistor with high concentration channel injection region A gate insulating film and gate electrodes are formed on a substrate containing N-type impurities such as P or As. Under the gate insulating film is a gate region on both sides of which are a first and a second source drain region. The gate region is furn... | 06/27/2000 |
| 6057592 | Compound semiconductor epitaxial wafer At the time of forming an alloy composition gradient layer 4 of gallium arsenide phosphide GaAsx P1-x having an arsenic alloy composition x changed in such a range as not to exceed a predetermined alloy composition a with an increase... | 05/02/2000 |
| 5977611 | Power diode and hybrid diode, voltage limiter and freewheeling diode having the power diode A Read diode includes an inner zone, a cathode zone, an anode zone and a first coupling zone disposed between the inner zone and the anode zone. A second coupling zone is disposed between the first coupling zone and the inner zone. Both coupling zones are... | 11/02/1999 |
| 5932894 | SiC semiconductor device comprising a pn junction A semiconductor device of planar structure, comprises a pn junction, formed of a first type conducting layer and on top thereof a second type conducting layer, both layers of doped silicon carbide, the edge of the second of the layers being provided with ... | 08/03/1999 |
| 5899714 | Fabrication of semiconductor structure having two levels of buried regions Integrated circuits suitable for high-performance applications, especially mixed signal products that have analog and digital sections, are fabricated from a semiconductor structure in which lower buried regions of opposite conductivity types are situated... | 05/04/1999 |
| 5869886 | Flip chip semiconductor mounting structure with electrically conductive resin A semiconductor chip is flip chip bonded on a substrate wherein the semiconductor chip has a first surface on which bumps are provided. An insulating sealing resin is provided in a space defined between the semiconductor chip and the substrate and also ar... | 02/09/1999 |
| 5831297 | Structure of metal-insulator-semiconductor-like mutiple-negative-differential-resistance device The present invention provides a structure of a metal-insulator-semiconductor (MIS)-like multiple-negative-differential-resistance (MNDR) device and the fabrication method thereof. The device of the present invention has the characteristics of dual-r... | 11/03/1998 |
| 5811873 | Diode having soft recovery characteristics over a wide range of operating conditions A diode has a semiconductor layer which has a predetermined impurity concentration, and in which the rate of extension of a depletion layer during a reverse recovery operation gradually decreases so as to decrease the rate of change in reverse recovery cu... | 09/22/1998 |
| 5801836 | Depletion region stopper for PN junction in silicon carbide A semiconductor component comprises a pn junction having a first conductivity type layer and a second conductivity type layer, both being doped layers of silicon carbide (SiC), the first conductivity type layer being lower doped and being provided with a ... | 09/01/1998 |
| 5773858 | Power diode A power diode includes at least one semiconductor body having an inner zone f a first conductivity type and a given doping level, a cathode zone of the first conductivity type and a doping level higher than the given doping level, and an anode zone of a se... | 06/30/1998 |
| 5717244 | Semiconductor device having layers with varying lifetime characteristics An N- layer (11) of a low impurity concentration is formed on an upper major surface of an N+ layer (13) of a high impurity concentration in a diode (10). A P layer (12) is further formed on its upper major surface. The N-... | 02/10/1998 |
| 5701020 | Pseudomorphic step-doped-channel field-effect transistor A pseudomorphic step-doped-channel field-effect transistor is provided, which has advantages of large transconductance, high electron mobility, high gate voltage swing and high current density, and can increase the pinch-off voltage tolerance. Thus the ps... | 12/23/1997 |
