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| Number | Title | Issue Date |
| 8138582 | Impurity introducing apparatus having feedback mechanism using optical characteristics of impurity introducing region An impurity doping system is disclosed, which includes an impurity doping device for doping an impurity into a surface of a solid state base body, a measuring device for measuring an optical characteristic of an area into which the impurity is doped, and an annealin... | 03/20/2012 |
| 8134224 | Radio frequency semiconductor device A semiconductor device receiving as input a radio frequency signal having a frequency of 500 MHz or more and a power of 20 dBm or more is provided. The semiconductor device includes: a silicon substrate; a silicon oxide film formed on the silicon substrate; a radio ... | 03/13/2012 |
| 8030740 | Deposited semiconductor structure to minimize N-type dopant diffusion and method of making A microelectronic structure including a layerstack is provided, the layerstack including: (a) a first layer including semiconductor material that is very heavily n-doped before being annealed, having a first-layer before-anneal dopant concentration, the first layer ... | 10/04/2011 |
| 7936051 | Silicon wafer and its manufacturing method A silicon wafer which achieves a gettering effect without occurrence of slip dislocations is provided, and the silicon wafer is subject to heat treatment after slicing from a silicon monocrystal ingot so that a layer which has zero light scattering defects according... | 05/03/2011 |
| 7838969 | Diode A diode is disclosed. One embodiment provides a semiconductor body having a front and a back, opposite the front in a vertical direction of the semiconductor body. The semiconductor body contains, successively in the vertical direction from the back to the front, a ... | 11/23/2010 |
| 7656011 | Diode A diode is disclosed. One embodiment provides a semiconductor body having a front and a back, opposite the front in a vertical direction of the semiconductor body. The semiconductor body contains, successively in the vertical direction from the back to the front, a ... | 02/02/2010 |
| 7649244 | Vertical semiconductor device having semiconductor zones for improved operability under dynamic processes A vertical semiconductor device comprises a semiconductor body, a first contact and a second contact, wherein a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type and a third semiconductor region of a... | 01/19/2010 |
| 7569914 | Semiconductor devices and method of manufacturing them With conventional device, the quantity of complex defects differs with each semiconductor device because the concentration of impurities intrinsically contained differs for each silicon wafer. Consequently, there is an undesirable variation in characteristics among ... | 08/04/2009 |
| 7566951 | Silicon structures with improved resistance to radiation events A silicon structure with improved protection against failures induced by excess radiation-induced charge carrier migration from the bulk region into the near-surface region. The structure comprises bulk and near-surface regions that are doped with a dopant, wherein ... | 07/28/2009 |
| 7439592 | ESD protection for high voltage applications An ESD device includes a low doped well connected to a first contact and a diffusion area connected to a second contact. A substrate between the low doped well and the diffusion area has a dopant polarity that is opposite a dopant polarity of the low doped well and ... | 10/21/2008 |
| 7432538 | Field-effect transistor A field-effect transistor includes a channel layer having a channel and a carrier supply layer, disposed on the channel layer, containing a semiconductor represented by the formula AlxGa1-xN, wherein x is greater than 0.04 and less than 0.45. T... | 10/07/2008 |
| 7365402 | LDMOS transistor An LDMOS semiconductor transistor structure comprises a substrate having an epitaxial layer of a first conductivity type, a source region extending from a surface of the epitaxial layer of a second conductivity type, a lightly doped drain region within the epitaxial... | 04/29/2008 |
| 7319250 | Semiconductor component and method for producing the same A method for producing a semiconductor component has the following step: the front side (101) of the semiconductor body (100) is irradiated with high-energy particles using the terminal electrode (40) as a mask, in order to produce recombination... | 01/15/2008 |
| 7317242 | Semiconductor device including p-type silicon layer including implanted germanium The invention provides a semiconductor device having a pn diode that includes a p-type SiGe layer and a n-type Si layer junctioned to the p-type SiGe layer. A built-in potential of the pn diode can be reduced, and thus obtaining a diode characteristics with lower im... | 01/08/2008 |
| 7268079 | Method for fabricating a semiconductor having a field zone A method for fabricating a semiconductor and at least one second semiconductor zone of a semiconductor component having a semiconductor body having a first semiconductor zone. At least one field zone arranged in an edge region of the semiconductor body is reduced in... | 09/11/2007 |
| 7189771 | Electrically conducting organic polymer/nanoparticle composites and methods for use thereof Compositions are provided comprising aqueous dispersions of electrically conducting organic polymers and a plurality of nanoparticles. Films cast from invention compositions are useful as buffer layers in organic electronic devices, such as organic light emitting di... | 03/13/2007 |
| 7180132 | Enhanced RESURF HVPMOS device with stacked hetero-doping RIM and gradual drift region An HV PMOS device formed on a substrate having an HV well of a first polarity type formed in an epitaxial layer of a second polarity type includes a pair of field oxide regions on the substrate and at least partially over the HV well. Insulated gates are formed on t... | 02/20/2007 |
| 7166890 | Superjunction device with improved ruggedness An improved superjunction semiconductor device includes a charged balanced pylon in a body region, where a top of the pylon is large to create slight charge imbalance. A MOSgated structure is formed over the top of the pylon and designed to conduct current through t... | 01/23/2007 |
| 7163891 | High density DRAM with reduced peripheral device area and method of manufacture A dynamic random access memory (DRAM) structure having a distance less than 0.14 um between the contacts to silicon and the gate conductor is disclosed. In addition a method for forming the structure is disclosed, which includes forming the DRAM array contacts and t... | 01/16/2007 |
| 7138697 | Structure for and method of fabricating a high-speed CMOS-compatible Ge-on-insulator photodetector The invention addresses the problem of creating a high-speed, high-efficiency photodetector that is compatible with Si CMOS technology. The structure consists of a Ge absorbing layer on a thin SOI substrate, and utilizes isolation regions, alternating n- and p-type ... | 11/21/2006 |
| 7091579 | Power semiconductor rectifier having broad buffer structure and method of manufacturing thereof Impurity concentration (Nd(X)) in an n-drift layer in a diode is at a maximum at a position at a distance Xp from an anode electrode in a direction from the anode electrode to a cathode electrode, and gradually decreases from the position toward each of t... | 08/15/2006 |
| 7071504 | Thin film transistor device and method of manufacturing the same A semiconductor film into which p-type impurities have been introduced is formed on a substrate. Subsequently, a resist film is formed on the semiconductor film, and dry etching is performed to the semiconductor film using the resist film as a mask. Due to the dry e... | 07/04/2006 |
| 7071018 | Process for manufacturing a solar cell Process for incorporating a back surface field into a silicon solar cell by depositing a layer of aluminium on the rear surface of the cell, sintering the aluminium at a temperature between 700 and 1000° C., exposing the cell to an atmosphere of a compound of Group... | 07/04/2006 |
| 7064386 | Thin film transistor and fabricating method thereof Thin film transistors and methods of fabricating thin film transistors having low OFF state leakage current. The OFF state leakage current reduction is achieved by using doping implantation energies such that the average penetration depth of the doping impurity into... | 06/20/2006 |
| 7064385 | DMOS-transistor with lateral dopant gradient in drift region and method of producing the same A DMOS-transistor has a trench bordered by a drift region including two doped wall regions and a doped floor region extending along the walls and the floor of the trench. The laterally extending floor region has a dopant concentration gradient in the lateral directi... | 06/20/2006 |
| 7064399 | Advanced CMOS using super steep retrograde wells The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50) and source and drain regions (80) of a MOS tran... | 06/20/2006 |
| 7061058 | Forming a retrograde well in a transistor to enhance performance of the transistor A method of forming a retrograde well in a transistor is provided. A transistor structure having a substrate, a gate, and a gate oxide layer between the substrate and the gate is formed. The substrate includes a channel region located generally below the gate. A fir... | 06/13/2006 |
| 7045876 | Amorphizing ion implant method for forming polysilicon emitter bipolar transistor A method for fabricating a polysilicon emitter bipolar transistor employs a pair of ion implant methods. A first of the ion implant methods implants a portion of an intrinsic base region interposed between an extrinsic base region and a polysilicon emitter layer wit... | 05/16/2006 |
| 7037789 | Stabilization of dopant concentration in semiconductor device having epitaxially-filled trench A method for manufacturing a semiconductor device includes: forming a trench in a predetermined layer of a semiconductor substrate; heating the substrate having the trench in a non-oxidizing and non-nitridizing atmosphere containing a dopant or a compound that inclu... | 05/02/2006 |
| 7038326 | IC chip packaging for reducing bond wire length An integrated circuit packaging assembly for reducing the length of bond wires transmitting radio frequency signals is disclosed herein. The die is offset in the packaging to position a subset of its bond pads in close proximity to package bond pads to allow for sho... | 05/02/2006 |
| 7034364 | Reduced finger end MOSFET breakdown voltage (BV) for electrostatic discharge (ESD) protection The present invention relates to electro static discharge (ESD) protection circuitry. Multiple techniques are presented to adjust one or more ends of one or more fingers of an ESD protection device so that the ends of the fingers have a reduced initial trigger or br... | 04/25/2006 |
| 7030464 | Semiconductor device and method of manufacturing the same A technology of restraining junction leakage in a semiconductor device is to be provided. There is provided a semiconductor device provided with a semiconductor substrate, a gate electrode 9 formed on the semiconductor substrate, and a source/drain region for... | 04/18/2006 |
| 7005725 | Discrete component comprising HF diodes in series with a common cathode An electric component comprising an assembly of two PIN diodes in series formed in a semiconductor substrate layer separated from a support layer by an insulating layer, the doped areas forming the electrodes of each diode having a depth equal to that of the substra... | 02/28/2006 |
| 6956277 | Diode junction poly fuse System and method for providing an electrical fuse having a p-n junction diode. A preferred embodiment comprises a cathode, an anode, and one or more links formed between the cathode and the anode. The cathode and the portion of the cathode adjoining the link are do... | 10/18/2005 |
| 6909157 | Thermal nitrogen distribution method to improve uniformity of highly doped ultra-thin gate capacitors Methods such as Remote Plasma Nitridation (RPN) are used to introduce nitrogen into a gate dielectric layer. However, these methods yield nitrided layers where the layers are not uniform, both in cross-sectional profile and in nitrogen profile. Subjecting the nitrid... | 06/21/2005 |
| 6905891 | Method for processing multiple semiconductor devices for test A packaged array (10) having a temporary substrate (20) is used to test a plurality of semiconductor devices (14). In one embodiment, the temporary substrate (20) is an adhesive substrate, such as tape. A support structure (18) may... | 06/14/2005 |
| 6897500 | CMOS image sensor An example CMOS image sensor has pixel units and protection regions. The pixel unit has a light sensing region for converting an incident light into an electrical signal and an active region for controlling the transfer of the electrical signal. Each pixel unit is i... | 05/24/2005 |
| 6891238 | Semiconductor device and method of manufacturing the same A semiconductor device including a silicon substrate, a gate insulator film formed on the silicon substrate and including silicon, deuterium, and at least one of oxygen and nitrogen, and a gate electrode formed on the gate insulator film wherein a deuterium concentr... | 05/10/2005 |
| 6888207 | High voltage transistors with graded extension High voltage transistors with high breakdown voltages are provided. These high voltage transistors are formed with graded drain extension regions. The concentration of charge carriers increases farther away from the gate across each drain extension region, causing s... | 05/03/2005 |
| 6806548 | Semiconductor device To attain reduction in size of a semiconductor device having a power transistor and an SBD, a semiconductor device according to the present invention comprises a first region and a second region formed on a main surface of a semiconductor substrate; plural first con... | 10/19/2004 |
