Bizarre Patents
Mouthguard made at least partially from an edible candy
A mouthguard includes a U-shaped upper bite plate which removably fits over upper teeth of a person, with the entire upper bite plate being made from a soft, deformable and edible gummi candy.
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| Number | Title | Issue Date |
| 8138581 | Semiconductor device with channel stop trench and method A semiconductor device is provided which includes a semiconductor substrate having a first surface, an active area and a peripheral area. The semiconductor device further includes least one channel stop trench formed in the semiconductor substrate, wherein the chann... | 03/20/2012 |
| 7304354 | Buried guard ring and radiation hardened isolation structures and fabrication methods Semiconductor devices can be fabricated using conventional designs and process but including specialized structures to reduce or eliminate detrimental effects caused by various forms of radiation. Such semiconductor devices can include the one or more parasitic isol... | 12/04/2007 |
| 7288786 | Integrated circuit configuration with analysis protection and method for producing the configuration During the creation of wiring plans for logic modules, the regions which are left free of interconnects by synthesis methods in upper metal planes are filled to a maximum degree with further interconnects. These interconnects serve to protect the integrated circuit.... | 10/30/2007 |
| 7242063 | Symmetric non-intrusive and covert technique to render a transistor permanently non-operable A technique for and structures for camouflaging an integrated circuit structure. The technique including forming active areas of a first conductivity type and LDD regions of a second conductivity type resulting in a transistor that is always non-operational when sta... | 07/10/2007 |
| 7220994 | In plane switching mode liquid crystal display device A method for fabricating an in-plane switching LCD device includes forming a data line and a light-shielding layer on a substrate, forming a pixel electrode line and an active region with a polycrystalline silicon thin film, forming a first insulating layer on the s... | 05/22/2007 |
| 7217977 | Covert transformation of transistor properties as a circuit protection method A technique for and structures for camouflaging an integrated circuit structure. The technique includes the use of a light density dopant (LDD) region of opposite type from the active regions resulting in a transistor that is always off when standard voltages are ap... | 05/15/2007 |
| 7166515 | Implanted hidden interconnections in a semiconductor device for preventing reverse engineering A camouflaged interconnection for interconnecting two spaced-apart regions of a common conductivity type in an integrated circuit or device and a method of forming same. The camouflaged interconnection comprises a first region forming a conducting channel between th... | 01/23/2007 |
| 7151306 | Electronic part, and electronic part mounting element and an process for manufacturing such the articles A surface of an external electrode 3 of an electronic part 4 is formed with a coating containing resin ingredient. Thereby, adhesion strength and reliability may be significantly improved in mounting an electronic part onto a circuit board 1 thr... | 12/19/2006 |
| 7119413 | High-voltage transistor having shielding gate A semiconductor device includes a plurality of high-voltage insulated-gate field-effect transistors arranged in a matrix form on the main surface of a semiconductor substrate and each having a gate electrode, a gate electrode contact formed on the gate electrode, an... | 10/10/2006 |
| 7049667 | Conductive channel pseudo block process and circuit to inhibit reverse engineering A technique for and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed by a plurality of layers of material having a controlled outline. A layer of conductive material having a controlled outline is disposed among... | 05/23/2006 |
| 7042049 | Composite etching stop in semiconductor process integration A new method of forming a composite etching stop layer is described. An etching stop layer is deposited on a substrate wherein the etching stop layer is selected from the group consisting of: silicon carbide, silicon nitride, SiCN, SiOC, and SiOCN. A TEOS oxide laye... | 05/09/2006 |
| 6979606 | Use of silicon block process step to camouflage a false transistor A technique for and structures for camouflaging an integrated circuit structure. A layer of conductive material having a controlled outline is disposed to provide artifact edges of the conductive material that resemble an operable device when in fact the device is n... | 12/27/2005 |
| 6969660 | Method of manufacturing a semiconductor device with trench isolation between two regions having different gate insulating films The major surface of a semiconductor substrate of a semiconductor device includes first and second regions and a boundary area therebetween. A first gate insulating film and a first gate electrode are formed in the first region. A second gate insulating film differe... | 11/29/2005 |
| 6953961 | DRAM structure and fabricating method thereof A dynamic random access memory (DRAM) structure and a fabricating process thereof are provided. In the fabricating process, a channel region is formed with a doped region having identical conductivity as the substrate in a section adjacent to an isolation structure.... | 10/11/2005 |
| 6940764 | Memory with a bit line block and/or a word line block for preventing reverse engineering A method and circuit for blocking unauthorized access to at least one memory cell in a semiconductor memory. The method includes providing a switch and/or a link which assumes an open state when access to the at least one memory cell is to be blocked; and coupling-a... | 09/06/2005 |
| 6924228 | Method of forming a via contact structure using a dual damascene technique A method of forming a via contact structure using a dual damascene technique is provided. The method includes forming a lower interconnection line on a semiconductor substrate and sequentially forming an inter-metal dielectric layer and a hard mask layer on the semi... | 08/02/2005 |
| 6919600 | Permanently on transistor implemented using a double polysilicon layer CMOS process with buried contact A permanently-ON MOS transistor comprises silicon source and drain regions of a first conductivity type in a silicon well region of a second conductivity type. A silicon contact region of the first conductivity types is buried in the well region, said contact region... | 07/19/2005 |
| 6914320 | Bilayer HDP CVD/PE CVD cap in advanced BEOL interconnect structures and method thereof An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a bilayer diffusion barrier or cap, where the first cap layer is formed of a dielectric material preferably deposited by a high density plasma chemical vapor deposition ... | 07/05/2005 |
| 6887783 | Bilayer HDP CVD/PE CVD cap in advance BEOL interconnect structures and method thereof An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a bilayer diffusion barrier or cap, where the first cap layer is formed of a dielectric material preferably deposited by a high density plasma chemical vapor deposition ... | 05/03/2005 |
| 6667553 | H:SiOC coated substrates This invention pertains to a method for producing hydrogenated silicon oxycarbide (H:SiOC) films having low dielectric constant and a light transmittance of 95% or more for light with a wavelength in the range of 400 nm to 800 nm. The method comprises rea... | 12/23/2003 |
| 6593655 | Method for producing hydrogenated silicon oxycarbide films having low dielectric constant This invention pertains to a method for producing hydrogenated silicon oxycarbide (H:SiOC) films having low dielectric constant. The method comprises reacting an methyl-containing silane in a controlled oxygen environment using plasma enhanced or ozone as... | 07/15/2003 |
| 6563197 | MOSgated device termination with guard rings under field plate Guard ring diffusions in the termination of a MOSgated device are laterally spaced from one another and are disposed beneath and are insulated from the termination field plate which extends from the periphery of the device active area.... | 05/13/2003 |
| 6518635 | Semiconductor device and manufacturing method thereof A major object of the present invention is to provide an improved semiconductor device so as to be able to reduce gate electric field concentration at a channel edge, suppress decrease in the threshold during MOSFET operation and reduce the leakage curren... | 02/11/2003 |
| 6501155 | Semiconductor apparatus and process for manufacturing the same To provide a semiconductor apparatus that secures high ESD protection capability and yet reduces leak current. Cut sections 64-1 and 64-2 are provided in end sections of a second edge 62 of a drain region 22. When a distance between a first edge 60 of a source... | 12/31/2002 |
| 6465867 | Amorphous and gradated barrier layer for integrated circuit interconnects An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer... | 10/15/2002 |
| 6452285 | Fabrication of standard defects in contacts Various circuit devices for contact defect inspection and methods of fabrication and use thereof are provided. In one aspect, a circuit device is provided that includes a substrate and an insulating film positioned on the substrate that has a plurality of... | 09/17/2002 |
| 6333548 | Semiconductor device with etch stopping film There are provided a semiconductor device and a method for manufacturing the same in which a thin film polysilicon film having a small parasitic capacitance which is required for attaining the high-speed operation and high reliability can be used as a res... | 12/25/2001 |
| 6215167 | Power semiconductor device employing field plate and manufacturing method thereof A power semiconductor device having an breakdown voltage improving structure and a manufacturing method thereof are provided. A collector region and a base region create a pn junction between them. At least one accelerating region of the same conductivity... | 04/10/2001 |
| 6211541 | Article for de-embedding parasitics in integrated circuits An article for de-embedding parasitics and/or acting as an on-wafer calibration standard is disclosed. In particular, some articles in accordance with the present invention provide structures on integrated circuits that mitigate the severity of parasitics... | 04/03/2001 |
| 6194750 | Integrated circuit comprising means for high frequency signal transmission An integrated circuit is disclosed that comprises structures that confine, shield and/or manipulate the electric fields generated within the integrated circuit so as to improve the performance of the integrated circuit. Such structures include, but are no... | 02/27/2001 |
| 6153920 | Process for controlling dopant diffusion in a semiconductor layer and semiconductor device formed thereby A semiconductor device having a carbon-containing region with an advantageous concentration profile is disclosed. The carbon is introduced into a region of the substrate and at a depth below the space-charge layer of the device and at a concentration such... | 11/28/2000 |
| 6084263 | Power device having high breakdown voltage and method of manufacturing the same The main characteristic feature of the invention is to prevent a leakage current from flowing when a planar type semiconductor device having a high breakdown voltage is reverse-biased. For example, a semiconductive film is formed on the surface of an n-ty... | 07/04/2000 |
| 6064110 | Digital circuit with transistor geometry and channel stops providing camouflage against reverse engineering An integrated digital circuit is protected from reverse engineering by fabricating all transistors of like conductivity with a common size and geometric layout, providing a common layout for different logic cells, connecting doped circuit elements of like... | 05/16/2000 |
| 6054752 | Semiconductor device A semiconductor device comprises a semiconductor substrate including a first conductivity type first semiconductor layer and a second conductivity type second semiconductor layer formed on the first semiconductor layer. A unit cell for controlling current... | 04/25/2000 |
| 5726469 | Surface voltage sustaining structure for semiconductor devices A surface voltage sustaining structure around an n+ (or p+)-type region on a p- (or n-)-type substrate for high-voltage devices is made by a combination of n-type regions and/or p-type regions and produces an ... | 03/10/1998 |
| 5712492 | Transistor for checking radiation-hardened transistor A checking transistor for checking selected regions a semiconductor substrate containing radiation-hardened semiconductor circuitry having a plurality of transistors according to the present invention comprises a source region of the other conductivity ty... | 01/27/1998 |
| 5641982 | High voltage mosfet with an improved channel stopper structure The present invention provides a MOS field effect transistor comprising: a semiconductor substrate having a first conductivity type; source/drain regions of a second conductivity type; lightly doped regions covering the bottom of the source/drain regions ... | 06/24/1997 |
| 5631496 | Semiconductor component having a passivation layer and method for manufacturing same A semiconductor component has a semiconductor body with at least on pn-junction therein, extending to the surface of the semiconductor body, and has a passivation layer composed of boron-doped, amorphous, hydrogenous carbon (A-C:H) which covers at least t... | 05/20/1997 |
| 5541435 | Integration of high voltage lateral MOS devices in low voltage CMOS architecture using CMOS-compatible process steps Region forming steps or interconnect-forming steps through which low voltage CMOS devices are formed in a semiconductor wafer are also employed to simultaneously form one or more regions or layers at selected sites of a substrate where high voltage device... | 07/30/1996 |
| 5508555 | Thin film field effect transistor having a doped sub-channel region A thin film field effect transistor (1) is formed by an insulating substrate (2,3) carrying a semiconductor layer (4) having a polycrystalline channel region (5) which is passivated to reduce the density of charge carrier traps. Source and drain electrode... | 04/16/1996 |
