Did You Know...
...that power steering was invented by independent inventor Francis W. Davis? As chief engineer in the 1920s of the truck division of the Pierce Arrow Motor Car Company, he saw how hard it was to steer heavy vehicles. So that he would be able to keep the profits from his future invention, Davis left his job, rented a small engineering shop in Waltham, Mass., and developed a hydraulic power steering system that led to power steering.
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| Number | Title | Issue Date |
| 7414823 | Holder for use in semiconductor or liquid-crystal manufacturing device and semiconductor or liquid-crystal manufacturing device in which the holder is installed Affords a holder for use in semiconductor or liquid-crystal manufacturing devices—as well as semiconductor or liquid-crystal manufacturing devices in which the holder is installed—in which temperature uniformity in the processed-object retaining face is heighten... | 08/19/2008 |
| 7271468 | High-voltage compatible, full-depleted CCD A charge coupled device for detecting electromagnetic and particle radiation is described. The device includes a high-resistivity semiconductor substrate, buried channel regions, gate electrode circuitry, and amplifier circuitry. For good spatial resolution and high... | 09/18/2007 |
| 7227254 | Integrated circuit package A packaged IC includes an IC die with signal and signal complement traces positioned relative to each other to maximize broadside coupling for a matching impedance. The signal and signal complement traces are electrically connected to transmission or receive channel... | 06/05/2007 |
| 7163903 | Method for making a semiconductor structure using silicon germanium A semiconductor substrate having a silicon layer is provided. In one embodiment, the substrate is a silicon-on-insulator (SOI) substrate having an oxide layer underlying the silicon layer. An amorphous or polycrystalline silicon germanium layer is formed overlying t... | 01/16/2007 |
| 7038313 | Semiconductor device and method of manufacturing the same A semiconductor device includes a circuit board formed of an insulator substrate and having conductor patterns on both surfaces thereof, a semiconductor chip bonded to the circuit board with one of the conductor patterns therebetween, and a radiator base bonded to t... | 05/02/2006 |
| 6956281 | Semiconductor device for reducing photovolatic current A semiconductor device that has a common border between P and N wells is susceptible to photovoltaic current that is believed to be primarily generated from photons that strike this common border. Photons that strike the border are believed to create electron/hole p... | 10/18/2005 |
| 6953961 | DRAM structure and fabricating method thereof A dynamic random access memory (DRAM) structure and a fabricating process thereof are provided. In the fabricating process, a channel region is formed with a doped region having identical conductivity as the substrate in a section adjacent to an isolation structure.... | 10/11/2005 |
| 6894354 | Trench isolated transistors, trench isolation structures, memory cells, and DRAMs An isolation trench in a semiconductor includes a first isolation trench portion having a first depth and having a first sidewall intersecting a surface of the semiconductor at a first angle. A second isolation trench portion extends within and below the first isola... | 05/17/2005 |
| 6770917 | High-voltage diode A high-voltage diode and a method for producing the high-voltage diode involve only three masking steps. Only three masking steps are required due to the use of adjustment structures and of a chipping stopper with an edge passivation containing a-C:H or a-Si. In thi... | 08/03/2004 |
| 6639279 | Semiconductor transistor having interface layer between semiconductor and insulating layers The present invention provides a semiconductor device capable of preventing deterioration in carrier mobility of a semiconductor layer, which is a quality of the interface between the semiconductor layer and an insulating layer, and a method of manufactur... | 10/28/2003 |
| 6600524 | Active matrix type liquid crystal display apparatus with silicon oxide at different portions An improved liquid crystal display apparatus for low power consumption has a thin film transistor as a switching device. The thin film transistor has a gate insulating layer of laminated film of silicon nitride and silicon oxide, a semiconductor layer, a ... | 07/29/2003 |
| 6518635 | Semiconductor device and manufacturing method thereof A major object of the present invention is to provide an improved semiconductor device so as to be able to reduce gate electric field concentration at a channel edge, suppress decrease in the threshold during MOSFET operation and reduce the leakage curren... | 02/11/2003 |
| 6501155 | Semiconductor apparatus and process for manufacturing the same To provide a semiconductor apparatus that secures high ESD protection capability and yet reduces leak current. Cut sections 64-1 and 64-2 are provided in end sections of a second edge 62 of a drain region 22. When a distance between a first edge 60 of a source... | 12/31/2002 |
| 6469329 | Solid state image sensing device and method of producing the same A solid state image sensing device comprises a cell area, located at a semiconductor substrate, including photoelectric conversion portions and charge transfer portions and a peripheral circuit area formed around the cell area located at the semiconductor... | 10/22/2002 |
| 6373121 | Silicon chip built-in inductor structure A silicon chip built-in inductor structure. The structure at least includes a substrate, a plurality of active devices on the substrate, a dielectric layer with a planarized upper surface and an inductor device. The substrate can be divided into an active... | 04/16/2002 |
| 6323539 | High voltage integrated circuit, high voltage junction terminating structure, and high voltage MIS transistor A high voltage integrated circuit is provided that includes a first region of first conductivity type; a second region of second conductivity type formed in a first major surface of the first region; a third region of first conductivity type formed in a s... | 11/27/2001 |
| 6320245 | Radiation-hardened semiconductor device Boron ions are implanted in the boundary of the field oxide film and P type well, and a first high energy boron implantation P layer is formed. Further boron ions are implanted near the center of the field oxide film in the thickness direction, and a seco... | 11/20/2001 |
| 6285073 | Contact structure and method of formation The horizontal surface area required to contact semiconductor devices, in integrated circuits fabricated with trench isolation, is minimized without degrading contact resistance by utilizing the vertical surface area of the trench sidewall. A trench isola... | 09/04/2001 |
| 6249036 | Stepper alignment mark formation with dual field oxide process A semiconductor photomask set for producing wafer alignment accuracy in a semiconductor fabrication process. The photomask set produces an alignment mark that is accurate for subsequent fabrication after undergoing a dual field oxide (FOX) fabrication pro... | 06/19/2001 |
| 6242782 | Circuit for providing isolation of integrated circuit active areas The provision of an isolation gate connecting unassociated active areas of adjacent transistors formed in a semiconductor substrate provides effective isolation of the adjacent transistors with no additional process steps required. The isolation gate is t... | 06/05/2001 |
| 6229202 | Semiconductor package having downset leadframe for reducing package bow A bow resistant semiconductor package includes a semiconductor die, a leadframe segment and a plastic body. The leadframe segment includes lead fingers attached and wire bonded to the die, and opposing volume equalizing members proximate to lateral edges ... | 05/08/2001 |
| 6127708 | Semiconductor device having an intervening region between channel stopper and diffusion region In a method for manufacturing a semiconductor device, an anti-oxidation layer is formed on a semiconductor substrate of a first conductivity type. Then, a first photoresist pattern layer for defining an active area is formed on the anti-oxidation layer, a... | 10/03/2000 |
| 6124628 | High voltage integrated circuit, high voltage junction terminating structure, and high voltage MIS transistor A high voltage integrated circuit is provided that includes a first region of first conductivity type; a second region of second conductivity type formed in a first major surface of the first region; a third region of first conductivity type formed in a s... | 09/26/2000 |
| 6091133 | Assembly of a semiconductor device and paddleless lead frame having tape extending between the lead fingers A semiconductor integrated circuit device, and method of manufacturing the same, having a conventional-type lead frame with the die paddle removed. In particular, the die paddle is replaced with a section of tape that is supported by the ends of the lead ... | 07/18/2000 |
| 6046483 | Planar isolation structure in an integrated circuit A method is provided for forming an isolation structure at a semiconducting surface of a body, and the isolation structure formed thereby. A masking layer is formed over selected regions of the substrate surface; the masking layer preferably comprising a ... | 04/04/2000 |
| 6034410 | MOSFET structure with planar surface A method is provided for a planar surface of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A conductive layer is formed over a substrate. A silicon nitride layer is formed over the conductive layer. A photores... | 03/07/2000 |
| 5973375 | Camouflaged circuit structure with step implants Connections between implanted regions in a semiconductor substrate, such as the sources or drains of adjacent transistors, are made by buried conductive implants rather than upper level metalizations. The presence or absence of a connection between two im... | 10/26/1999 |
| 5874769 | Mosfet isolation structure with planar surface A method is provided for a planar surface of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A conductive layer is formed over a substrate. A silicon nitride layer is formed over the conductive layer. A photores... | 02/23/1999 |
| 5841169 | Integrated circuit containing devices dielectrically isolated and junction isolated from a substrate An integrated circuit comprises a plurality of interconnected semiconductor devices, at least one the interconnected devices being dielectrically isolated from the substrate, and at least one other of the interconnected devices being junction isolated fro... | 11/24/1998 |
| 5804884 | Surface electrical field delimiting structure for an integrated circuit The resin sealing layer enclosing the device is biased to a low voltage by means of an anchoring structure formed close to high-voltage contact pads. The anchoring structure is formed by a metal region deposited on the surface of the device and contacting... | 09/08/1998 |
| 5729049 | Tape under frame for conventional-type IC package assembly A semiconductor integrated circuit device, and method of manufacturing the same, having a conventional-type lead frame with the die paddle removed. In particular, the die paddle is replaced with a section of tape that is supported by the ends of the lead ... | 03/17/1998 |
| 5696400 | MOS-type semiconductor integrated circuit device A semiconductor integrated circuit device comprises an input terminal for inputting a voltage, an output terminal for outputting a voltage, a MOS driver disposed between the input terminal and the output terminal for adjusting the voltage of the input ter... | 12/09/1997 |
| 5693976 | MOSFET device having denuded zones for forming alignment marks A process for fabricating MOSFET devices, in which a denuded zone in silicon has been created during the normal process sequence, has been developed. In order to avoid the formation of deleterious oxygen precipitates, prior to the creation of the denuded ... | 12/02/1997 |
| 5545907 | Semiconductor device and method of forming the same A semiconductor device includes a semiconductor substrate, element isolation films, channel stop diffusion layers, and elements formed on the semiconductor substrate in spaced-apart relation from each other by means of the element isolation films. The ele... | 08/13/1996 |
| 5541435 | Integration of high voltage lateral MOS devices in low voltage CMOS architecture using CMOS-compatible process steps Region forming steps or interconnect-forming steps through which low voltage CMOS devices are formed in a semiconductor wafer are also employed to simultaneously form one or more regions or layers at selected sites of a substrate where high voltage device... | 07/30/1996 |
| 5483096 | Photo sensor A photo sensor comprises a semiconductor substrate, a bipolar photo transistor having an emitter region, a base region and a collector region which is formed in the surface region of the semiconductor substrate, a silicon dioxide formed on the bipolar pho... | 01/09/1996 |
| 5401998 | Trench isolation using doped sidewalls A P-type substrate is immersed in a solution of potassium hydroxide (KOH) which etches exposed portions of the substrate to form trenches with sidewalls at an angle of 54.7 degrees with respect to the top surface of the substrate. A vertical boron implant... | 03/28/1995 |
| 5373177 | Semiconductor device with improved electric charge storage characteristics A semiconductor device such as a DRAM is provided, in which a channel stop region of a first conductive type is formed in a semiconductor substrate just below a field insulator. The channel stop region comprises a first part and a second part higher in im... | 12/13/1994 |
| 5365082 | MOSFET cell array A CMOS memory cell array, and a process for making it, that avoids problems caused by LOCOS isolation of cells. Moats are formed by etching away columns of a thick field oxide layer. The moats have two-tiered sidewalls, such that an upper tier is sloped, ... | 11/15/1994 |
| 5350942 | Low resistance silicided substrate contact Low resistance contacts for establishing an electrical pathway to an integrated surface substrate are provided. The pathway is formed by the connection of a p+ doped channel stop region with a p+ doped extrinsic layer. P+ doped polysilicon contacts are po... | 09/27/1994 |
