Did You Know...
...that on Dec. 15, 1836, the Patent Office was completely destroyed by fire? Lost were some 7,000 models, 9,000 drawings, and 230 books plus all records of patent applications and grants.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 7923821 | Semiconductor integrated circuit substrate containing isolation structures Isolation regions for semiconductor substrates include dielectric-filled trenches and field oxide regions. Protective caps of dielectric materials dissimilar from the dielectric materials in the main portions of the trenches and field oxide regions may be used to pr... | 04/12/2011 |
| 7626246 | Solutions for integrated circuit integration of alternative active area materials Methods of forming areas of alternative material on crystalline semiconductor substrates, and structures formed thereby. Such areas of alternative material are suitable for use as active areas in MOSFETs or other electronic or opto-electronic devices. ... | 12/01/2009 |
| 7508053 | Semiconductor MOS transistor device and method for making the same A method of manufacturing a metal-oxide-semiconductor (MOS) transistor device is disclosed. A gate dielectric layer is formed on an active area of a substrate. A gate electrode is patterned on the gate dielectric layer. The gate electrode has vertical sidewalls and ... | 03/24/2009 |
| 7358596 | Device isolation for semiconductor devices Exemplary embodiments of the present invention disclose a semiconductor assembly having at least one isolation structure formed. The semiconductor assembly comprises: a first trench in a semiconductive substrate; a second trench extending the overall trench depth in... | 04/15/2008 |
| 7358144 | Method for fabricating semiconductor device A method for fabricating a semiconductor device includes forming first, second, and third device structures in a semiconductor substrate. Each device structure includes a first film, a second film over the first film, and a third film over the second film. The first... | 04/15/2008 |
| 7323387 | Method to make nano structure below 25 nanometer with high uniformity on large scale A method of making a nano structure smaller than 25 nanometers utilizing atomic layer deposition, planarizing, and etching techniques. ... | 01/29/2008 |
| 7279769 | Semiconductor device and manufacturing method thereof To suppress occurrence of dislocation in a substrate of a semiconductor device at an end portion of a gate electrode. Provided is a semiconductor device having a plurality of element formation regions formed over the main surface of a semiconductor substrate, an ele... | 10/09/2007 |
| 7268402 | Memory cell with trench-isolated transistor including first and second isolation trenches An isolation trench in a semiconductor includes a first isolation trench portion having a first depth and having a first sidewall intersecting a surface of the semiconductor at a first angle. A second isolation trench portion extends within and below the first isola... | 09/11/2007 |
| 7262489 | Three-dimensionally formed circuit sheet, component and method for manufacturing the same A three-dimensionally formed circuit sheet comprises a resin film and a circuit pattern formed of an electrically conductive paste on the resin film. The electrically conductive paste contains, as a binder, a resin that is three-dimensionally formable. The resin fil... | 08/28/2007 |
| 7259076 | High-density SOI cross-point memory fabricating method A method for fabricating a high-density silicon-on-insulator (SOI) cross-point memory array and an array structure are provided. The method includes the following steps: selectively forming a hard mask on an SOI substrate, defining memory areas, active device areas,... | 08/21/2007 |
| RE39690 | Enhanced planarization technique for an integrated circuit A method for planarizing integrated circuit topographies, wherein, after a first layer of spin-on glass is deposited, a layer of low-temperature oxide is deposited before a second layer of spin-on glass. ... | 06/12/2007 |
| 7199012 | Method of forming a trench in a semiconductor device A method for forming a trench in a semiconductor device is disclosed. An example method forms a pad oxide film and a silicon nitride film on a semiconductor substrate, selectively etches the silicon nitride film and the pad oxide film on a region to be formed with a... | 04/03/2007 |
| 7199450 | Materials and method to seal vias in silicon substrates Sealing a via using a soventless, low viscosity, high temperature stable polymer or a high solids content polymer solution of low viscosity, where the polymeric material is impregnated within the via at an elevated temperature. A supply chamber is introduced to admi... | 04/03/2007 |
| 7190045 | Semiconductor device and method for fabricating the same A semiconductor device is composed of: an interconnect made of a first conductive film and a second conductive film that are stacked in sequence from the interconnect underside on an insulating film formed on a substrate; and a capacitor composed of a lower capacito... | 03/13/2007 |
| 7190051 | Chip level hermetic and biocompatible electronics package using SOI wafers The invention is directed to a hermetically packaged and implantable integrated circuit for electronics that is made by producing streets in silicon-on-insulator chips that are subsequently coated with a selected electrically insulating thin film prior to completing... | 03/13/2007 |
| 7176549 | Shallow trench isolation using low dielectric constant insulator A shallow trench isolation is disclosed wherein the trench depth is reduced beyond that achieved in prior art processes. The reduced trench depth helps to eliminate the formation of voids during the trench refill process and provides for greater planarity in the fin... | 02/13/2007 |
| 7148546 | MOS transistor gates with doped silicide and methods for making the same Semiconductor devices and fabrication methods are presented, in which transistor gate structures are created using doped metal silicide materials. Upper and lower metal silicides are formed above a gate dielectric, wherein the lower metal silicide is doped with n-ty... | 12/12/2006 |
| 7145166 | CMOSFET with hybrid strained channels Disclosed is a method of manufacturing microelectronic devices including forming a silicon substrate with first and second wells of different dopant characteristics, forming a first strained silicon-germanium-carbon layer of a first formulation proximate to the firs... | 12/05/2006 |
| 7135381 | Wet etching method of removing silicon from a substrate and method of forming trench isolation A wet etching method of removing silicon from a substrate includes depositing a layer comprising silicon in elemental form over a substrate. The layer is exposed to an aqueous liquid etching solution comprising a hydroxide and a fluoride, and having a pH of at least... | 11/14/2006 |
| 7112975 | Advanced probe card and method of fabricating same In one embodiment, an anti-wafer structure includes a silicon on insulator (SOI) layer and a plurality of probe dice formed on the SOI layer. Each of the probe die may have a pad layout corresponding to a pad layout of a die on a wafer under test. A plurality of hol... | 09/26/2006 |
| 7067890 | Thick oxide region in a semiconductor device A method of forming an oxide region in a semiconductor device includes the steps of forming a plurality of trenches in a semiconductor layer of the device, the trenches being formed in close relative proximity to one another, and oxidizing the semiconductor layer su... | 06/27/2006 |
| 7049206 | Device isolation for semiconductor devices Exemplary embodiments of the present invention disclose a semiconductor assembly having at least one isolation structure formed. The semiconductor assembly comprises: a first trench in a semiconductive substrate; a second trench extending the overall trench depth in... | 05/23/2006 |
| 7045434 | Semiconductor device and method for manufacturing the same A method for manufacturing a semiconductor substrate including a mask aligning trench. The method includes forming the mask aligning trench and an element partitioning trench. The element partitioning and mask aligning trenches are filled with insulation. The insula... | 05/16/2006 |
| 7009271 | Memory device with an alternating Vss interconnection A semiconductor memory device provides non-volatile memory with a memory array having an alternating Vss interconnection. Using the alternating Vss interconnection, a low implant dosage is added to a region proximate to the lower areas of an STI region, such as bene... | 03/07/2006 |
| 7005712 | Method for manufacturing a semiconductor device A semiconductor device of the present invention includes a semiconductor layer 10, an insulation gate type heavy insulated transistor 200 and an insulation gate type light insulated transistor 300 having different drain-source breakdown voltages... | 02/28/2006 |
| 6979878 | Isolation structure having implanted silicon atoms at the top corner of the isolation trench filling vacancies and interstitial sites A method for isolating a first active region from a second active region, both of which are configured within a semiconductor substrate. The method comprises forming a dielectric masking layer above a semiconductor substrate. An opening is then formed through the ma... | 12/27/2005 |
| 6979876 | Method for forming isolation layer of semiconductor device A method for forming an isolation layer of a semiconductor device which is capable of improving isolation characteristics of a highly integrated semiconductor device. The method includes the steps of forming a first insulating layer on a substrate; forming both a fi... | 12/27/2005 |
| 6972477 | Circuit device with conductive patterns separated by insulating resin-filled grooves To make thin a circuit device 10 in which are incorporated a plurality of types of circuit elements 12 that differ in thickness, first conductive patterns, onto which comparatively thin circuit elements 12A are mounted, are formed thickly, and s... | 12/06/2005 |
| 6972242 | Methods to fabricate semiconductor devices Semiconductor device fabrication methods are disclosed. According to one example, a method includes forming a pad oxide layer and a nitride layer sequentially on a silicon substrate, and forming a photoresist pattern for trench formation on the nitride layer; etchin... | 12/06/2005 |
| 6962856 | Method for forming device isolation film of semiconductor device A method for forming a device isolation film of a semiconductor device, wherein an annealing process is performed on the oxide film using NH3 prior to the deposition of a liner nitride film and after the deposition of a thermal oxide film on a sidewall of a trench t... | 11/08/2005 |
| 6953961 | DRAM structure and fabricating method thereof A dynamic random access memory (DRAM) structure and a fabricating process thereof are provided. In the fabricating process, a channel region is formed with a doped region having identical conductivity as the substrate in a section adjacent to an isolation structure.... | 10/11/2005 |
| 6940171 | Multi-layer dielectric and method of forming same A multiple dielectric device and its method of manufacture overlaying a semiconductor material, including a substrate, an opening relative to the substrate, the opening having an aspect ratio greater than about two, a first dielectric layer in the opening, wherein a... | 09/06/2005 |
| 6933211 | Semiconductor device whose semiconductor chip has chamfered backside surface edges and method of manufacturing the same A semiconductor element is formed in the major surface of a semiconductor chip. Curved surfaces having a radius of curvature of 0.5 to 50 μm are formed at at least some of edges where the side surfaces and backside surface of the semiconductor chip cross. ... | 08/23/2005 |
| 6924555 | Specially shaped contact via and integrated circuit therewith An integrated circuit device including a contact via having a non-cylindrical bottom portion is disclosed. Also a contact via with non-parallel side walls is disclosed. The contact vias are selectively positioned in the integrated circuit device. ... | 08/02/2005 |
| 6894354 | Trench isolated transistors, trench isolation structures, memory cells, and DRAMs An isolation trench in a semiconductor includes a first isolation trench portion having a first depth and having a first sidewall intersecting a surface of the semiconductor at a first angle. A second isolation trench portion extends within and below the first isola... | 05/17/2005 |
| 6849928 | Dual silicon-on-insulator device wafer die A silicon-on-insulator semiconductor device is provided in which a single wafer die contains a transistor over an insulator layer to form a fully depleted silicon-on-insulator device and a transistor formed in a semiconductor island over an insulator structure on th... | 02/01/2005 |
| 6847098 | Non-floating body device with enhanced performance A method of forming a buried silicon oxide region in a semiconductor substrate with portions of the buried silicon oxide region formed underlying portions of a strained silicon shape, and where the strained silicon shape is used to accommodate a semiconductor device... | 01/25/2005 |
| 6812572 | Bit line landing pad and borderless contact on bit line stud with localized etch stop layer formed in void region, and manufacturing method thereof An etch-stop layer is selectively provided between layers of a multiple-layered circuit in a selective manner so as to allow for outgassing of impurities during subsequent fabrication processes. The etch-stop layer is formed over an underlying stud so as to serve as... | 11/02/2004 |
| 6809402 | Reflowable-doped HDP film Device leakage due to spacer undercutting is remedied by depositing a B-doped HDP or a BP-doped HDP oxide gap filling layer capable of flowing into undercut regions. Embodiments include depositing a B or BP-doped HDP oxide film containing 4 to 6 wt. % B over closely... | 10/26/2004 |
| 6794719 | HV-SOI LDMOS device with integrated diode to improve reliability and avalanche ruggedness A hybrid semiconductor device is presented in which one or more diode regions are integrated into a transistor region. In a preferred embodiment the transistor region is a continuous (self-terminating) SOI LDMOS device in which are integrated one or more diode porti... | 09/21/2004 |
