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| Number | Title | Issue Date |
| 7485949 | Semiconductor device A semiconductor device is disclosed. The device includes a substrate, a first porous SiCOH dielectric layer, a second porous SiCOH dielectric layer, and an oxide layer. The first porous SiCOH dielectric layer overlies the substrate. The second porous SiCOH dielectri... | 02/03/2009 |
| 7405466 | Method of fabricating microelectromechanical system structures A method of simultaneously bonding components, comprising the following steps. At least first, second and third components are provided and comprise: at least one glass component; and at least one conductive or semiconductive material component. The order of stackin... | 07/29/2008 |
| 7368793 | HEMT transistor semiconductor device The semiconductor device of the present invention includes a device formation region formed on a substrate and including at least one semiconductor region, and a first electrode and a second electrode formed spaced apart from each other on the device formation regio... | 05/06/2008 |
| 7357977 | Ultralow dielectric constant layer with controlled biaxial stress A method for forming a ultralow dielectric constant layer with controlled biaxial stress is described incorporating the steps of forming a layer containing Si, C, O and H by one of PECVD and spin-on coating and curing the film in an environment containing very low c... | 04/15/2008 |
| 7348268 | Controlled breakdown phase change memory device A phase change memory material may be deposited over an electrode in a pore through an insulator. The adherence of the memory material to the insulator may be improved by using a glue layer. At the same time, a breakdown layer may be formed in the pore between the m... | 03/25/2008 |
| 7321145 | Method and apparatus for operating nonvolatile memory cells with modified band structure A nonvolatile memory cell with a charge storage structure is read by measuring current (such as band-to-band current) between the substrate region of the memory cell and at least one of the current carrying nodes of the memory cell. To enhance the operation of the n... | 01/22/2008 |
| 7314801 | Semiconductor device having a surface conducting channel and method of forming A semiconductor device including a metal oxide layer, a channel area of the metal oxide layer, a preservation layer formed on the channel area of the metal oxide layer, and at least two channel contacts coupled to the channel area of the metal oxide layer, and a met... | 01/01/2008 |
| 7298024 | Transparent amorphous carbon structure in semiconductor devices A transparent amorphous carbon layer is formed. The transparent amorphous carbon layer has a low absorption coefficient such that the amorphous carbon is transparent in visible light. The transparent amorphous carbon layer may be used in semiconductor devices for di... | 11/20/2007 |
| 7282774 | Semiconductor device and method for manufacturing semiconductor device A semiconductor device comprising a semiconductor substrate, a gate dielectrics formed on the semiconductor substrate and including a silicon oxide film containing a metallic element, the silicon oxide film containing the metallic element including a first region ne... | 10/16/2007 |
| 7268052 | Method for reducing soft error rates of memory cells In one embodiment, a method of fabricating a transistor for a memory cell includes the steps of performing a counter doping implant before or after a source/drain implant. The counter doping implant may comprise one or more implant steps that move a metallurgical ju... | 09/11/2007 |
| 7259055 | Method of forming high-luminescence silicon electroluminescence device A method for forming a high-luminescence Si electroluminescence (EL) phosphor is provided, with an EL device made from the Si phosphor. The method comprises: depositing a silicon-rich oxide (SRO) film, with Si nanocrystals, having a refractive index in the range of ... | 08/21/2007 |
| 7259387 | Nonvolatile semiconductor memory device A nonvolatile memory element is formed by layering a lower electrode, a variable resistor and an upper electrode in sequence. The variable resistor is formed in which crystallinity and amorphism are mixed. Thus, the nonvolatile memory element is formed. More prefera... | 08/21/2007 |
| 7256098 | Method of manufacturing a memory device A method of making a memory device and a memory device is described. In one embodiment, a method of manufacturing a memory device is described. The method includes providing a substrate having a tunneling layer deposited on a main surface and having a first conducti... | 08/14/2007 |
| 7235865 | Methods for making nearly planar dielectric films in integrated circuits In the fabrication of integrated circuits, one specific technique for making surfaces flat is chemical-mechanical planarization. However, this technique is quite time consuming and expensive, particularly as applied to the numerous intermetal dielectric layers—the... | 06/26/2007 |
| 7221039 | Thin film transistor (TFT) device structure employing silicon rich silicon oxide passivation layer A thin film transistor device structure and a method for fabricating the thin film transistor device structure each comprise a thin film transistor device formed over a substrate. The thin film transistor device structure also comprises a passivation layer formed of... | 05/22/2007 |
| 7217954 | Silicon carbide semiconductor device and method for fabricating the same An inventive semiconductor device is provided with: a silicon carbide substrate 1; an n-type high resistance layer 2; well regions 3 provided in a surface region of the high resistance layer 2; a p+ contact region 4 prov... | 05/15/2007 |
| 7208426 | Preventing plasma induced damage resulting from high density plasma deposition A method and apparatus for preventing plasma induced damage resulting from high density plasma deposition processes. In the present embodiment, Un-doped Silica Glass(USG) is deposited so as to form a USG liner. In the present embodiment, the USG liner directly overl... | 04/24/2007 |
| 7205640 | Semiconductor device and display comprising same In an inverse-stagger MOSFET (1), a gate insulating layer (4) made of amorphous aluminum oxide is so formed as to face a channel layer (5) which serves as the semiconductor layer, and which is made of zinc oxide. With this arrangement, a defect ... | 04/17/2007 |
| 7202137 | Process for producing an integrated electronic circuit comprising superposed components and integrated electronic circuit thus obtained A process for producing an integrated electronic circuit. The process begins with the production of a first electronic component and a second electronic component that are superposed on top of a substrate. A volume of temporary material is formed on the substrate at... | 04/10/2007 |
| 7187058 | Semiconductor component having a pn junction and a passivation layer applied on a surface The invention relates to a semiconductor component having a semiconductor body (100) and at least one pn junction present in the semiconductor body (100) and an amorphous passivation layer (70) arranged at least in sections on a surface (101 | 03/06/2007 |
| 7161224 | Complete device layer transfer without edge exclusion via direct wafer bonding and constrained bond-strengthening process More complete bonding of wafers may be achieved out to the edge regions of the wafer by constrained bond strengthening of the wafers in a pressure bonding apparatus after direct wafer bonding. The pressure bonding process may be accompanied by the application of not... | 01/09/2007 |
| 7145172 | Thin film transistor array substrate A thin film transistor array substrate of a thin film transistor liquid crystal display (TFT-LCD) is provided. The gate dielectric layer of the TFT includes a silicon nitride layer, a dielectric layer and a silicon nitride layer, and the etching selectivity of the a... | 12/05/2006 |
| 7134197 | Plastic lead frames utilizing reel-to-reel processing Reel-to-reel manufacturing methods and systems are disclosed herein. In general, one or more plastic parts (e.g., plastic substrate) can be transported on a carrier for manufacturing of a final product based initially on the part or substrate. A reel-to-reel mechani... | 11/14/2006 |
| 7119353 | Electric device with phase change material and method of manufacturing the same The electric device (100) has a body (102) having a resistor (107) comprising a phase change material being changeable between a first phase and a second phase. The resistor (107) has a first electrical resistance when the phase change ma... | 10/10/2006 |
| 7105895 | Epitaxial SiObarrier/insulation layer A method for producing an insulating or barrier layer (FIG. 1B), useful for semiconductor devices, comprises depositing a layer of silicon and at least one additional element on a silicon substrate whereby said deposited layer is substantially free of defects... | 09/12/2006 |
| 7105914 | Integrated circuit and seed layers Structures are provided which improve performance in integrated circuits. The structures include a diffusion barrier and a seed layer in an integrated circuit both formed using a low energy ion implantation followed by a selective deposition of metal lines for the i... | 09/12/2006 |
| 7087503 | Shallow self isolated doped implanted silicon process A process and structure for forming electrical devices. The process and structure provide for forming an insulating layer on a substrate. A conductive region is then formed in the insulating layer by implanting silicon atoms into the insulating layer. Further, a plu... | 08/08/2006 |
| 7078342 | Method of forming a gate stack A method for forming a gate stack which minimizes or eliminates damage to the gate dielectric layer and/or silicon substrate during the gate stack formation by the reduction of the temperature during formation. The temperature reduction prevents the formation of sil... | 07/18/2006 |
| 7067414 | Low k interlevel dielectric layer fabrication methods A low k inter-level dielectric layer fabrication method includes providing a substrate having integrated circuitry at least partially formed thereon. An oxide-comprising inter-level dielectric layer including carbon and having a dielectric constant no greater than 3... | 06/27/2006 |
| 7045865 | Semiconductor device with resistor elements formed on insulating film A semiconductor device of the invention has a plurality of resistor elements formed on an element isolating oxide film in predetermined regions on a surface of a semiconductor substrate. Active regions are furnished close to the resistor elements. This allows the el... | 05/16/2006 |
| 7045277 | Semiconductor processing methods of transferring patterns from patterned photoresists to materials, and structures comprising silicon nitride The invention includes a semiconductor processing method. A first material comprising silicon and nitrogen is formed. A second material is formed over the first material, and the second material comprises silicon and less nitrogen, by atom percent, than the first ma... | 05/16/2006 |
| 7041548 | Methods of forming a gate stack that is void of silicon clusters within a metallic silicide film thereof A method for forming a gate stack which minimizes or eliminates damage to the gate dielectric layer and/or silicon substrate during the gate stack formation by the reduction of the temperature during formation. The temperature reduction prevents the formation of sil... | 05/09/2006 |
| 7030468 | Low k and ultra low k SiCOH dielectric films and methods to form the same Dielectric materials including elements of Si, C, O and H having specific values of mechanical properties (tensile stress, elastic modulus, hardness cohesive strength, crack velocity in water) that result in a stable ultra low k film which is not degraded by water v... | 04/18/2006 |
| 7030429 | Hetero-junction bipolar transistor and the method for producing the same This invention provides a hetero-junction bipolar transistor with a new structure that prevent the corrector resistance from increasing as shrinking the size of the transistor. The bipolar transistor according to the invention comprises a substrate 2, a colle... | 04/18/2006 |
| 7015168 | Low dielectric constant fluorine and carbon-containing silicon oxide dielectric material characterized by improved resistance to oxidation The invention provides a process for forming a low k fluorine and carbon-containing silicon oxide dielectric material by reacting with an oxidizing agent one or more silanes containing one or more organofluoro silanes having the formula SiR1R2R... | 03/21/2006 |
| 6984843 | Board for electronic device, electronic device, ferroelectric memory, electronic apparatus, ink-jet recording head, and ink-jet printer A board for an electronic device is provide comprising a substrate having an amorphous layer, a buffer layer formed on the amorphous layer, the buffer layer having an orientation at least in the direction of its thickness, and a conductive oxide layer formed on the ... | 01/10/2006 |
| 6978434 | Method of designing wiring structure of semiconductor device and wiring structure designed accordingly A wiring structure of a semiconductor device, includes a wiring layer formed on an insulating film, a width (W) of each wire in the wiring layer and a thickness (H) of the insulating film satisfying “W/H | 12/20/2005 |
| 6977407 | Even nucleation between silicon and oxide surfaces for thin silicon nitride film growth A method of providing even nucleation between silicon and oxide surfaces for growing uniformly thin silicon nitride layers used in semiconductor devices. First, a nonconductive nitride-nucleation enhancing monolayer is formed over a semiconductor assembly having bot... | 12/20/2005 |
| 6959920 | Protection against in-process charging in silicon-oxide-nitride-oxide-silicon (SONOS) memories A pre-metal dielectric structure of a SONOS memory structure includes a UV light-absorbing film, which prevents the ONO structure from being electronically charged in response to UV irradiation. In one embodiment, the pre-metal dielectric structure includes a first ... | 11/01/2005 |
| 6933177 | Aluminum leadframes for semiconductor devices and method of fabrication A leadframe for use with integrated circuit chips comprising a leadframe base made of aluminum or aluminum alloy having a surface layer of zinc; a first layer of nickel on said zinc layer, said first nickel layer deposited to be compatible with aluminum and zinc; a ... | 08/23/2005 |
