Class 257/640 - At least one layer of silicon nitride

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: Subject matter wherein there is at least one layer of silicon
No. of patents: 494
Last issue date: 09/27/2011

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Number	Title	Issue Date
6252297	Array substrate, liquid crystal display device and their manufacturing method An array substrate typically used in a liquid crystal display device includes inter-layer insulating films thick enough to prevent step-off breakage of conductive layers at contact holes while promising a reliability. Thick inter-layer insulating films ar...	06/26/2001
6252295	Adhesion of silicon carbide films The adhesion of a silicon carbide containing film to a surface is enhanced by employing a transition film of silicon nitride, silicon dioxide and/or silicon oxynitride....	06/26/2001
6246105	Semiconductor device and manufacturing process thereof A semiconductor device having an insulation protection film with increased reliability and improved device characteristics, and a manufacturing method thereof which improves the planarization and reduces the interlayer capacitance of the device. The semic...	06/12/2001
6246076	Layered dielectric on silicon carbide semiconductor structures A dielectric structure is disclosed for silicon carbide-based semiconductor devices. In gated devices, the structure includes a layer of silicon carbide, a layer of silicon dioxide on the silicon carbide layer, a layer of another insulating material on th...	06/12/2001
6232663	Semiconductor device having interlayer insulator and method for fabricating thereof A semiconductor device and a method of fabricating thereof, including an insulator layer having alternately layered insulator films and boundary layers, wherein the boundary layers are more dense than the insulator films to prevent expansion and elongatio...	05/15/2001
6232218	Etch stop for use in etching of silicon oxide A etch stop layer for use in a silicon oxide dry fluorine etch process is made of silicon nitride with hydrogen incorporated in it either in the form of N--H bonds, O--H bonds, or entrapped free hydrogen. The etch stop layer is made by either increasing t...	05/15/2001
6232641	Semiconductor apparatus having elevated source and drain structure and manufacturing method therefor A semiconductor apparatus on which a MOS transistor having an elevated source and drain structure is formed is arranged to have a gate electrode which is formed on the surface of a silicon substrate through an insulating film. An elevated source film and ...	05/15/2001
6229192	Image sensor or LCD including switching pin diodes A method of manufacturing a PIN (positive-intrinsic-negative) diode structure includes depositing an insulation or dielectric layer over the bottom PIN diode electrodes, prior to depositing the PIN semiconductor layers. The insulation layer results in a P...	05/08/2001
6225671	Method of reducing defects in anti-reflective coatings and semiconductor structures fabricated thereby A method of fabricating a substantially smooth-surfaced anti-reflective coating on a semiconductor device structure including generating a plasma from an inert gas in a process chamber in which the substantially smooth anti-reflective coating is to be dep...	05/01/2001
6222257	Etch stop for use in etching of silicon oxide A etch stop layer for use in a silicon oxide dry fluorine etch process is made of silicon nitride with hydrogen incorporated in it either in the form of N--H bonds, Si--H bonds, or entrapped free hydrogen. The etch stop layer is made by either increasing ...	04/24/2001
6222256	Semiconductor device and method of manufacturing the same A first layer metal wire, an SiOF film and an F diffusion prevention film are formed on a surface of a base layer including a substrate, elements formed on the substrate and an insulator layer formed to cover the substrate and the elements. The F diffusio...	04/24/2001
6215190	Borderless contact to diffusion with respect to gate conductor and methods for fabricating A borderless contact to diffusion with respect to gate conductor is provided by employing a double insulating film stack as a mask for defining the gate conductor shapes for the entire chip and providing a relatively thin damage preventing layer on expose...	04/10/2001
6214702	Methods of forming semiconductor substrates using wafer bonding techniques and intermediate substrates formed thereby Methods of forming semiconductor substrates include the steps of bonding a first semiconductor substrate to a second semiconductor substrate. The first semiconductor substrate has a first adhesion layer thereon extending opposite a first surface thereof a...	04/10/2001
6214713	Two step cap nitride deposition for forming gate electrodes A method for forming the gate electrode in an integrated circuit, in which a cap silicon nitride layer is deposited in a two step process to improve the condition of silicon nitride residue remaining on the surface of tungsten silicide. First, a layer of ...	04/10/2001
6211022	Field leakage by using a thin layer of nitride deposited by chemical vapor deposition A nitride layer is deposited over a field oxide layer used to separate transistors formed in a substrate, the nitride layer serving to decrease transistor current leakage. The nitride layer has a dense lattice, effectively blocking H+ and Na+ penetration ...	04/03/2001
6211537	LED array A 1200 dpi LED may be manufactured without highly accurate mask alignment and provide good light radiation efficiency. A first interlayer dielectric is formed on a semiconductor substrate and has a plurality of first windows formed therein and aligned in ...	04/03/2001
6198133	Electro-optical device having silicon nitride interlayer insulating film Using thin film transistors (TFTs), an active matrix circuit, a driver circuit for driving the active matrix circuit or the like are formed on one substrate. Circuits such as a central processing unit (CPU) and a memory, necessary to drive an electric dev...	03/06/2001
6191443	Capacitors, methods of forming capacitors, and DRAM memory cells Capacitors and methods of forming capacitors are disclosed. In one implementation, a capacitor comprises a capacitor dielectric layer comprising Ta2 O5 formed over a first capacitor electrode. A second capacitor electrode is formed o...	02/20/2001
6188125	Via formation in polymeric materials A semiconductor device and process for making the same are disclosed which use organic-containing materials to reduce capacitance between conductors, while allowing conventional photolithography and metal techniques and materials to be used in fabrication...	02/13/2001
6188101	Flash EPROM cell with reduced short channel effect and method for providing same Reduction in the short channel effect of a Flash EPROM cell is described. A method includes forming a gate structure on a substrate structure, and performing a nitrogen implant. Further included is performing device doping, wherein the nitrogen implant in...	02/13/2001
6184550	Ternary nitride-carbide barrier layers A microelectronic structure including adjacent material layers susceptible of adverse interaction in contact with one another, and a barrier layer interposed between said adjacent material layers, wherein said barrier layer comprises a binary, ternary or ...	02/06/2001
6180997	Structure for a multi-layered dielectric layer and manufacturing method thereof A manufacturing method and a structure of a multi-layered dielectric layer for forming openings in the dielectric layers for improving integration of integrated circuits, capability of step coverage, and problems caused by a structure of overhang, in whic...	01/30/2001
6180507	Method of forming interconnections A method of forming interconnections is provided. A defined metal layer is formed as a metal line on a provided substrate. An oxide layer is formed on the metal layer and on the substrate. A silicon nitride layer is formed on the oxide layer. The oxide la...	01/30/2001
6175147	Device isolation for semiconductor devices Exemplary embodiments of the present invention disclose a semiconductor assembly having at least one isolation structure formed. The semiconductor assembly comprises: a first trench in a semiconductive substrate; a second trench extending the overall tren...	01/16/2001
6169304	Semiconductor device having a passivation layer which minimizes diffusion of hydrogen into a dielectric layer A semiconductor device forming a capacitor through an interlayer insulating layer on a semiconductor substrate on which an integrated circuit is formed. This semiconductor device has an interlayer insulating layer with moisture content of 0.5 g/cm3	01/02/2001
6169293	Display device A resin material having a small relative dielectric constant is used as a layer insulation film 114. The resin material has a flat surface. A black matrix or masking film for thin film transistors is formed thereon using a metal material. Such a configura...	01/02/2001
6163049	Method of forming a composite interpoly gate dielectric The as-deposited thickness of at least one of the oxide layers of a composite ONO dielectric film between a floating gate and a control gate of a non-volatile semiconductor device is deposited to a sufficient thickness such that, after the top oxide layer...	12/19/2000
6144083	Method of reducing defects in anti-reflective coatings and semiconductor structures fabricated thereby A method of fabricating a substantially smooth-surfaced anti-reflective coating on a semiconductor device structure including generating a plasma from an inert gas in a process chamber in which the substantially smooth anti-reflective coating is to be dep...	11/07/2000
6137156	Semiconductor device employing silicon nitride layers with varied hydrogen concentration On a TEOS (tetraethyl ortho silicate) film and a surface of an aluminum wiring formed on a P-type silicon substrate, there is formed a low hydrogen content plasma SiN film on which a high hydrogen content plasma SiN film is laminated. The low hydrogen con...	10/24/2000
6137155	Planar guard ring An integrated circuit is provided. The integrated circuit includes a substrate and at least one dielectric layer and a metal layer formed upon the substrate. The at least one dielectric layer includes a terminal dielectric layer. The integrated circuit fu...	10/24/2000
6137125	Two layer hermetic-like coating for on-wafer encapsulatuon of GaAs MMIC's having flip-chip bonding capabilities The present invention is drawn to a 2-layer hermetic coating for on wafer encapsulation of GaAs monolithic microwave integrated circuits and the flip-chip mounting thereof. The present invention utilizes the properties of benzocyclobutene (BCB) for use in...	10/24/2000
6133620	Semiconductor device and process for fabricating the same A semiconductor device comprising a thin film transistor, and a process for fabricating the same, the process comprising: a first step of forming an island-like semiconductor layer, a gate insulating film covering the semiconductor layer, and a gate elect...	10/17/2000
6133613	Anti-reflection oxynitride film for tungsten-silicide substrates The present invention provides an anti-reflection film for lithographic application on tungsten-silicide containing substrate. In one embodiment of the present invention, a structure for improving lithography patterning in integrated circuit comprises a t...	10/17/2000
6110784	Method of integration of nitrogen bearing high K film A transistor and a method of making the same are provided. The transistor includes a substrate that has an upper surface and a gate dielectric layer positioned on the substrate that has a first quantity of nitrogen therein. A gate electrode is positioned ...	08/29/2000
6107670	Contact structure of semiconductor device Disclosed is a contact structure between the bit line and the source/drain region in an EEPROM. An element region is isolated by a trench type element isolation region in a silicon substrate. The source/drain region is formed in the portion of the element...	08/22/2000
6100572	Amorphous silicon combined with resurf region for termination for MOSgated device A termination structure for semiconductor devices and a process for fabricating the termination structure are described and include a layer of amorphous silicon for passivating and terminating the device junctions. The layer of amorphous silicon is deposi...	08/08/2000
6093956	Semiconductor wafer assemblies comprising silicon nitride, methods of forming silicon nitride, and methods of reducing stress on semiconductive wafers In one aspect, the invention includes a method of semiconductive wafer processing comprising forming a silicon nitride layer over a surface of a semiconductive wafer, the silicon nitride layer comprising at least two portions, one of the at least two port...	07/25/2000
6091082	Electrostatic discharge protection for integrated circuit sensor passivation A structure and method for creating an integrated circuit passivation (24) comprising, a circuit (16), a dielectric (18), and metal plates (20) over which an insulating layer (26) is disposed that electrically and hermetically isolates the circuit (16), a...	07/18/2000
6091132	Passivation for integrated circuit sensors A structure and method for creating an integrated circuit passivation comprising, a circuit (16) over which an insulating layer (26 and/or 28) is disposed that electrically and hermetically isolates the circuit (16) and a silicon carbide layer (30) to for...	07/18/2000
6087710	Semiconductor device having self-aligned contacts In a peripheral circuit region requiring a conductive path between layers at the periphery of a memory cell array region, a conductive path is provided, after removing a silicon nitride film used for self-alignment contact from the area of the contacting ...	07/11/2000

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Class 257/640 - At least one layer of silicon nitride