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| Number | Title | Issue Date |
| 8026578 | Barrier film and method of producing barrier film A barrier film formed on top of a substrate, a barrier film formed so as to cover a functional element region fabricated on top of a substrate, or a barrier film formed on both a substrate and a functional element region, wherein the barrier film includes at least o... | 09/27/2011 |
| 7948062 | Semiconductor device and method for manufacturing semiconductor device A semiconductor device including a compound semiconductor laminated structure having a plurality of compound semiconductor layers formed over a semiconductor substrate, a first insulation film covering at least a part of a surface of the compound semiconductor lamin... | 05/24/2011 |
| 7902640 | Dielectric layer and thin film transistor A dielectric layer including a film with silicon compound contain oxygen and a film with silicon compound contain nitrogen is provided. A ratio of Si—N group absorption intensity to a thickness of the film with silicon compound contain nitrogen in an FTIR spectrum... | 03/08/2011 |
| 7838968 | Semiconductor device and method of fabricating same There are disclosed TFTs having improved reliability. An interlayer dielectric film forming the TFTs is made of a silicon nitride film. Other interlayer dielectric films are also made of silicon nitride. The stresses inside the silicon nitride films forming these in... | 11/23/2010 |
| 7821109 | Stressed dielectric devices and methods of fabricating same A structure and a method of making the structure. The structure includes a field effect transistor including: a first and a second source/drain formed in a silicon substrate, the first and second source/drains spaced apart and separated by a channel region in the su... | 10/26/2010 |
| 7786553 | Method of fabricating semiconductor device Method of fabricating thin-film transistors in which contact with connecting electrodes becomes reliable. When contact holes are formed, the bottom insulating layer is subjected to a wet etching process, thus producing undercuttings inside the contact holes. In orde... | 08/31/2010 |
| 7626244 | Stressed dielectric devices and methods of fabricating same A structure and a method of making the structure. The structure includes a field effect transistor including: a first and a second source/drain formed in a silicon substrate, the first and second source/drains spaced apart and separated by a channel region in the su... | 12/01/2009 |
| 7586177 | Semiconductor-on-insulator silicon wafer A method of fabricating a semiconductor-on-insulator semiconductor wafer is described that includes providing first and second semiconductor substrates. A first insulating layer is formed on the first substrate with a first predetermined stress and a second insulati... | 09/08/2009 |
| 7446395 | Device having dual etch stop liner and protective layer The present invention provides a semiconductor device having dual nitride liners, a silicide layer, and a protective layer beneath one of the nitride liners for preventing the etching of the silicide layer. A first aspect of the invention provides a semiconductor de... | 11/04/2008 |
| 7442628 | Semiconductor laser manufacturing method A method for manufacturing a semiconductor laser. As a preparative step for coating an end face of a resonator with a dielectric film, a cleavage plane of a semiconductor laminated structure that is to be the end face is subjected to a plasma cleaning to prevent a c... | 10/28/2008 |
| 7397073 | Barrier dielectric stack for seam protection The present invention provides a semiconducting device including a gate dielectric atop a semiconducting substrate, the semiconducting substrate containing source and drain regions adjacent the gate dielectric; a gate conductor atop the gate dielectric; a conformal ... | 07/08/2008 |
| 7382662 | Twin insulator charge storage device operation and its fabrication method The invention proposes am improved twin MONOS memory device and its fabrication. The ONO layer is self-aligned to the control gate horizontally. The vertical insulator between the control gate and the word gate does not include a nitride layer. This prevents the pro... | 06/03/2008 |
| 7372113 | Semiconductor device and method of manufacturing the same Disclosed is a semiconductor device comprising a semiconductor substrate, a gate electrode, a first insulating film formed between the semiconductor substrate and the gate electrode, and a second insulating film formed along a top surface or a side surface of the ga... | 05/13/2008 |
| 7368804 | Method and apparatus of stress relief in semiconductor structures A method, apparatus and system are provided for relieving stress in the via structures of semiconductor structures whenever a linewidth below a via is larger than a ground-rule, including providing a via at least as large as the groundrule, providing a landing pad a... | 05/06/2008 |
| 7358595 | Method for manufacturing MOS transistor Disclosed is a method for fabricating a MOS transistor. The present method includes forming a buffer layer pattern including nitrogen on the semiconductor substrate; forming a gate insulating layer and a gate electrode on the exposed substrate surface; forming a LDD... | 04/15/2008 |
| 7352053 | Insulating layer having decreased dielectric constant and increased hardness A method of manufacturing a mechanically robust insulating layer, including forming a low-k dielectric layer having a first dielectric constant on a substrate and forming a carbon nitride cap layer on the low-k dielectric layer, the insulating layer thereby having a... | 04/01/2008 |
| 7335548 | Method of manufacturing metal-oxide-semiconductor transistor A method of manufacturing a metal-oxide-semiconductor transistor is provided. A substrate having a gate structure thereon is provided. A source/drain extension region is formed in the substrate on each side of the gate structure. Thereafter, a carbon-containing mate... | 02/26/2008 |
| 7332768 | Non-volatile memory devices Non-volatile memory devices are disclosed. In a first example non-volatile memory device, programming and erasing of the memory device is performed through the same insulating barrier without the use of a complex symmetrical structure. In the example device, program... | 02/19/2008 |
| 7315076 | Display device and manufacturing method of the same A display device is provided in which contact holes, each having a sidewall with an ideal tapered shape, are formed in a structure in which a silicon oxide film, a silicon nitride film and a silicon oxide film are stacked in the named order. The display device inclu... | 01/01/2008 |
| 7304386 | Semiconductor device having a multilayer wiring structure The present invention provides a semiconductor device having a multilayer wiring structure including a lower Cu buried-wiring layer, a SiC film, a SiOC film of 400 nm in thickness functioning as an interlayer insulating film, and an upper Cu buried-wiring layer elec... | 12/04/2007 |
| 7303946 | Method of manufacturing a semiconductor device using an oxidation process A method of manufacturing a MOS transistor incorporating a silicon oxide film serving as a gate insulating film and containing nitrogen and a polycrystalline silicon film serving as a gate electrode and containing a dopant and arranged such that the gate electrode i... | 12/04/2007 |
| 7292302 | Fringe field switching liquid crystal display and method for manufacturing the same Disclosed are a fringe field switching liquid crystal display (FFS-LCD) and a method for manufacturing the same. The FFS-LCD comprises upper and lower substrates opposed to each other at a predetermined distance; a liquid crystal layer intervened between the upper a... | 11/06/2007 |
| 7271464 | Liner for shallow trench isolation A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, a silicon nitride barrier is deposited into the trench. The silicon nitride layer has a high nitrogen content ... | 09/18/2007 |
| 7271463 | Trench insulation structures including an oxide liner that is thinner along the walls of the trench than along the base A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, a liner layer preferably is deposited into the trench. An anisotropic plasma process is then performed on the ... | 09/18/2007 |
| 7265064 | Semiconductor device with porous interlayer insulating film In a method of manufacturing a semiconductor device, semiconductor circuit elements or wiring patterns are formed on a semiconductor substrate then, a porous semiconductor oxide film is formed as an interlayer insulating film on the semiconductor substrate including... | 09/04/2007 |
| 7265431 | Imageable bottom anti-reflective coating for high resolution lithography A semiconductor wafer may be coated with an imageable anti-reflective coating. As a result, the coating may be removed using the same techniques used to remove overlying photoresists. This may overcome the difficulty of etching anti-reflective coatings using standar... | 09/04/2007 |
| 7253501 | High performance metallization cap layer A semiconductor device having a nonconductive cap layer comprising a first metal element. The nonconductive cap layer comprises a first metal nitride, a first metal oxide, or a first metal oxynitride over conductive lines and an insulating material between the condu... | 08/07/2007 |
| 7244644 | Undercut and residual spacer prevention for dual stressed layers Methods are disclosed for forming dual stressed layers in such a way that both undercutting and an undesirable residual spacer of the first-deposited stressed layer are prevented. In one embodiment, a method includes forming a first stressed silicon nitride layer ov... | 07/17/2007 |
| 7241661 | Method of forming a coupling dielectric TaOin a memory device A method of forming a coupling dielectric in a memory cell includes forming an oxide on a substrate, forming Ta2O5 on the oxide, oxidizing the Ta2O5 with rapid thermal process (RTP) at a temperature above the crystallizati... | 07/10/2007 |
| 7242096 | Semiconductor device and method for manufacturing the same The present invention provides a semiconductor device having a multilayer wiring structure including a lower Cu buried-wiring layer, a SiC film, a SiOC film of 400 nm in thickness functioning as an interlayer insulating film, and an upper Cu buried-wiring layer elec... | 07/10/2007 |
| 7233029 | Optical functional film, method of forming the same, and spatial light modulator, spatial light modulator array, image forming device and flat panel display using the same An optical functional film comprises a multilayer film formed by stacking a plurality of films. The plurality of films are formed by a same material and refractive indices of adjacent films are different. ... | 06/19/2007 |
| 7232969 | Keypad A keypad suitable for being disposed on a circuit board is provided. The keypad is in contact with the circuit board to generate an electrical signal. The keypad includes a flexible light guide plate, a key pattern, a passivation layer, a light source, and a reflect... | 06/19/2007 |
| 7202568 | Semiconductor passivation deposition process for interfacial adhesion A method of passivating an integrated circuit (IC) is provided. An insulating layer is formed onto the IC. An adhesion layer is formed onto a surface of the insulating layer by treating the surface of the insulating layer with a gas. A first passivation layer is for... | 04/10/2007 |
| 7199444 | Memory device, programmable resistance memory cell and memory array A method of metal doping a chalcogenide material includes forming a metal over a substrate. A chalcogenide material is formed on the metal. Irradiating is conducted through the chalcogenide material to the metal effective to break a chalcogenide bond of the chalcoge... | 04/03/2007 |
| 7192851 | Semiconductor laser manufacturing method A method for manufacturing a semiconductor laser. As a preparative step for coating an end face of a resonator with a dielectric film, a cleavage plane of a semiconductor laminated structure that is to be the end face is subjected to a plasma cleaning to prevent a c... | 03/20/2007 |
| 7190033 | CMOS device and method of manufacture A CMOS device and manufacturing method thereof wherein a bilayer etch stop is used over a PMOS transistor, and a single etch stop layer is used for an NMOS transistor, for forming contacts to the source or drain of the CMOS device. A surface tension-reducing layer i... | 03/13/2007 |
| 7179749 | Method for fabricating semiconductor device capable of decreasing critical dimension in peripheral region A method for fabricating a semiconductor device where a critical dimension in a peripheral region is decreased. The method includes the steps of: forming a silicon nitride layer on a substrate including a cell region and a peripheral region; forming a silicon oxynit... | 02/20/2007 |
| 7176523 | Power mosfet having conductor plug structured contacts In a high frequency amplifying MOSFET having a drain offset region, the size is reduced and the on-resistance is decreased by providing conductor plugs 13 (P1) for leading out electrodes on a source region 10, a drain region 9 and leach-t... | 02/13/2007 |
| 7173296 | Reduced hydrogen sidewall spacer oxide An embodiment of the invention is a method of making a semiconductor structure 10 where the spacer oxide layer 90 is formed by a hydrogen free precursor CVD process. Another embodiment of the invention is a semiconductor structure 10 having a sp... | 02/06/2007 |
| 7164189 | Slim spacer device and manufacturing method A CMOS structure including a Slim spacer and method for forming the same to reduce an S/D electrical resistance and improve charge mobility in a channel region, the method including providing a semiconductor substrate including a polysilicon gate structure including... | 01/16/2007 |
