Bizarre Patents
Mouse device with a built-in printer
A mouse device for use as an input device of a computer is provided that includes a housing in which recording paper is loadable, and a printer unit provided within the housing for printing on the recording paper print information received from the computer.
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| Number | Title | Issue Date |
| 7973391 | Tapered dielectric and conductor structures and applications thereof Disclosed are tapered dielectric and conductor structures which provide controlled impedance interconnection while signal conductor lines transition from finer pitches to coarser pitches thereby obviating electrical discontinuities generally associated with changes ... | 07/05/2011 |
| 7928537 | Organic electroluminescent device A functional device having, on a substrate, a pair of electrodes, a functional layer which is sandwiched between the electrodes and has an output that varies in accordance with an applied electric current, and a terminal arranged to apply an electric current to at l... | 04/19/2011 |
| 7745909 | Localized temperature control during rapid thermal anneal Disclosed are embodiments of a semiconductor structure and method of forming the structure with selectively adjusted reflectance and absorption characteristics in order to selectively control temperature changes during a rapid thermal anneal and, thereby, to selecti... | 06/29/2010 |
| 7679166 | Localized temperature control during rapid thermal anneal Disclosed herein are embodiments of a semiconductor structure and an associated method of forming the semiconductor structure with shallow trench isolation structures having selectively adjusted reflectance and absorption characteristics in order to ensure uniform t... | 03/16/2010 |
| 7470975 | Composition for forming insulation film, insulation film for semiconductor device, and fabrication method and semiconductor device thereof It is an object of the present invention to provide, with good yields, a composition for forming an insulation film which allows obtaining an insulation film for a semiconductor device having a low dielectric constant, excellent stress resistance and excellent crack... | 12/30/2008 |
| 7419897 | Method of fabricating circuit board having different electrical connection structures A method of fabricating an electrical connecting structure of a circuit board is disclosed. The method includes: providing a circuit board having a plurality of first and a plurality of second conductive pads; forming on the circuit board a solder mask having a plur... | 09/02/2008 |
| 7420264 | High reflector tunable stress coating, such as for a MEMS mirror An optical device having a high reflector tunable stress coating includes a micro-electromechanical system (MEMS) platform, a mirror disposed on the MEMS platform, and a multiple layer coating disposed on the mirror. The multiple layer coating includes a layer of si... | 09/02/2008 |
| 7397126 | Semiconductor device The present invention provides inhibiting an electrical leakage caused by anion migration. A trenched portion 15 is provided as ion migration-preventing zone between a source electrode 4 and a gate electrode 5. The trenched portion 15 is ... | 07/08/2008 |
| 7391094 | Semiconductor structure and method of making same A semiconductor structure includes a substrate having a surface and being made of a material that provides atypical surface properties to the surface, a bonding layer on the surface of the substrate, and a further layer molecularly bonded to the bonding layer. A met... | 06/24/2008 |
| 7388279 | Tapered dielectric and conductor structures and applications thereof Disclosed are tapered dielectric and conductor structures which provide controlled impedance interconnection while signal conductor lines transition from finer pitches to coarser pitches thereby obviating electrical discontinuities generally associated with changes ... | 06/17/2008 |
| 7385277 | Semiconductor chip and method of fabricating the same A semiconductor chip may include a semiconductor substrate that may have a semiconductor device pattern. A passivation layer may be provided on a surface of the semiconductor substrate. At least one elastic protecting layer may be provided on the passivation layer. ... | 06/10/2008 |
| 7339190 | Memory cell, pixel structure and fabrication process of memory cell A memory cell suitable for being disposed over a substrate is provided. The memory cell includes a poly-silicon island, a first dielectric layer, a trapping layer, a second dielectric layer and a control gate. The poly-silicon island is disposed on the substrate and... | 03/04/2008 |
| 7326987 | Non-continuous encapsulation layer for MIM capacitor The present invention relates to metal-insulator-metal (MIM) capacitors and field effect transistors (FETs) formed on a semiconductor substrate. The FETs are formed in Front End of Line (FEOL) levels below the MIM capacitors which are formed in upper Back End of Lin... | 02/05/2008 |
| 7319274 | Methods for selective integration of airgaps and devices made by such methods Methods for the production of airgaps in semiconductor devices and devices produced using such methods are disclosed. An example semiconductor device includes a damascene stack formed using such methods. The damascene stack includes a patterned dielectric layer incl... | 01/15/2008 |
| 7312400 | Multilayer wiring board, base for multilayer wiring board, printed wiring board and its manufacturing method A multilayer wiring board assembly component comprises: an insulating substrate component (the insulating resin layer 111); a conductive layer 112 formed on one surface of said insulating substrate component 111 in the form of an electrode patte... | 12/25/2007 |
| 7294935 | Integrated circuits protected against reverse engineering and method for fabricating the same using an apparent metal contact line terminating on field oxide Semiconducting devices, including integrated circuits, protected from reverse engineering comprising metal traces leading to field oxide. Metallization usually leads to the gate, source or drain areas of the circuit, but not to the insulating field oxide, thus misle... | 11/13/2007 |
| 7281667 | Method and structure for implementing secure multichip modules for encryption applications A tamper resistant, integrated circuit (IC) module includes a ceramic-based chip carrier, one or more integrated circuit chips attached to the chip carrier, and a cap structure attached to the chip carrier, covering the one or more integrated circuit chips. A conduc... | 10/16/2007 |
| 7280715 | Formation of cleaved grooves in a passivation layer formed over a surface of a wafer prior to wafer singulation Cleaved grooves, also referred to herein as “cleave streets”, are formed exclusively in a wafer passivation layer overlaying a wafer to provide for correctly aligned and sharp cleaves prior to singulation of the wafer into separate die or chips. The deployment o... | 10/09/2007 |
| 7259432 | Semiconductor device for reducing parasitic capacitance produced in the vicinity of a transistor located within the semiconductor device A semiconductor device includes: a gate electrode formed on a substrate; impurity regions formed in the substrate and to both sides of the gate electrode; a first interlayer insulating film formed to cover the gate electrode; and a second interlayer insulating film ... | 08/21/2007 |
| 7242063 | Symmetric non-intrusive and covert technique to render a transistor permanently non-operable A technique for and structures for camouflaging an integrated circuit structure. The technique including forming active areas of a first conductivity type and LDD regions of a second conductivity type resulting in a transistor that is always non-operational when sta... | 07/10/2007 |
| 7242021 | Semiconductor device and display element using semiconductor device The present invention achieves the enhancement of stability of operational performance of a display device and the enlargement of margin of design in circuit designing. In a semiconductor device including a semiconductor, a gate insulation film which is brought into... | 07/10/2007 |
| 7217977 | Covert transformation of transistor properties as a circuit protection method A technique for and structures for camouflaging an integrated circuit structure. The technique includes the use of a light density dopant (LDD) region of opposite type from the active regions resulting in a transistor that is always off when standard voltages are ap... | 05/15/2007 |
| 7214629 | Strain-silicon CMOS with dual-stressed film A semiconductor device has an NMOS portion and a PMOS portion. A first stress layer overlies a first channel to provide a first stress type to the channel and a first modified stress layer is formed from a portion of the first stress layer overlying a second channel... | 05/08/2007 |
| 7208836 | Integrated circuitry and a semiconductor processing method of forming a series of conductive lines A semiconductor processing method of forming a plurality of conductive lines includes, a) providing a substrate; b) providing a first conductive material layer over the substrate; c) providing a first insulating material layer over the first conductive layer; d) etc... | 04/24/2007 |
| 7205600 | Capacitor constructions with a barrier layer to threshold voltage shift inducing material A capacitor forming method can include forming an insulation layer over a substrate and forming a barrier layer to threshold voltage shift inducing material over the substrate. An opening can be formed at least into the insulation layer and a capacitor dielectric la... | 04/17/2007 |
| 7198993 | Method of fabricating a combined fully-depleted silicon-on-insulator (FD-SOI) and partially-depleted silicon-on-insulator (PD-SOI) devices A method (100) of forming fully-depleted (90) and partially-depleted (92) silicon-on-insulator (SOI) devices on a single die in an integrated circuit device (2) is disclosed using SOI starting material (4, 6, 8) and a selective epi... | 04/03/2007 |
| 7196422 | Low-dielectric constant structure with a multilayer stack of thin films with pores The present invention describes a structure having a multilayer stack of thin films, the thin films being a low-dielectric constant material, the thin films having pores, and a method of forming such a structure. ... | 03/27/2007 |
| 7190052 | Semiconductor devices with oxide coatings selectively positioned over exposed features including semiconductor material A semiconductor device structure includes a passivation layer through which only non-silicon-comprising structures are exposed. The semiconductor device structure is formed by selectively forming the passivation layer on an exposed silicon-comprising surface by expo... | 03/13/2007 |
| 7187038 | Semiconductor device with MOS transistors with an etch-stop layer having an improved residual stress level and method for fabricating such a semiconductor device A semiconductor device includes a substrate, MOS transistors in the substrate, and a dielectric layer on the MOS transistors. Contact holes are formed through the dielectric layer to provide electrical connection to the MOS transistors. An etch-stop layer is between... | 03/06/2007 |
| 7166515 | Implanted hidden interconnections in a semiconductor device for preventing reverse engineering A camouflaged interconnection for interconnecting two spaced-apart regions of a common conductivity type in an integrated circuit or device and a method of forming same. The camouflaged interconnection comprises a first region forming a conducting channel between th... | 01/23/2007 |
| 7164177 | Multi-level memory cell A multi-level memory cell including a substrate, a tunneling dielectric layer, a charge-trapping layer, a top dielectric layer, a gate and a pair of source/drain regions is provided. The tunneling dielectric layer, the charge-trapping layer and the top dielectric la... | 01/16/2007 |
| 7157380 | Damascene process for fabricating interconnect layers in an integrated circuit A damascene process using a doped and undoped oxide ILD is described. The selectivity between the carbon doped and carbon free oxide provides an etching stop between the ILD's in addition to providing mechanical strength to the structure. ... | 01/02/2007 |
| 7154373 | Surface mounting chip network component A surface mounting chip network component in which a network having three or more odd number of terminals are formed on the surface of an insulating substrate and Tomb Stone Phenomenon is suppressed. Even number of network circuits are formed on the surface of the i... | 12/26/2006 |
| 7145235 | Hermetic passivation structure with low capacitance A wafer passivation structure and its method of fabrication is described. According to one embodiment of the present invention a metal layer having a bond pad spaced by a gap from a metal member is formed on a substrate. A first dielectric layer is then formed over ... | 12/05/2006 |
| 7135758 | Surface mount solder method and apparatus for decoupling capacitance and process of making A system to package high performance microelectronic devices, such as processors, responds to component transients. In one embodiment, the system includes a decoupling capacitor that is disposed between a Vcc electrical bump and a Vss electrical bump. The decoupling... | 11/14/2006 |
| 7115995 | Structural reinforcement of highly porous low k dielectric films by Cu diffusion barrier structures Highly porous, low-k dielectric materials are mechanically reinforced to enable the use of these low-k materials as intralayer and interlayer dielectrics in advanced integrated circuits such as those which incorporate highly porous materials in a Cu damascene interc... | 10/03/2006 |
| 7112524 | Substrate for pre-soldering material and fabrication method thereof A substrate for a pre-soldering material and a fabrication method of the substrate are proposed. The substrate having at least one surface formed with a plurality of conductive pads is provided. An insulating layer is formed over the surface of the substrate in such... | 09/26/2006 |
| 7094657 | Method for protecting against oxidation of a conductive layer in said device In a semiconductor device including a first conductive layer, the first conductive layer is treated with a nitrogen/hydrogen plasma before an additional layer is deposited thereover. The treatment stuffs the surface with nitrogen, thereby preventing oxygen from bein... | 08/22/2006 |
| 7091615 | Concentration graded carbon doped oxide A process for forming an interlayer dielectric layer is disclosed. The method comprises first forming a carbon-doped oxide (CDO) layer with a first concentration of carbon dopants therein. Next, the CDO layer is further formed with a second concentration of carbon d... | 08/15/2006 |
| 7090554 | Fabrication of flat-panel display having spacer with rough face for inhibiting secondary electron escape A flat-panel display is fabricated by a process in which a spacer (24) having a rough face (54 or 56) is positioned between a pair of plate structure (20 and 22). When electrons strike the spacer, the roughness in the spacer's face... | 08/15/2006 |
