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| Number | Title | Issue Date |
| 8362596 | Engineered interconnect dielectric caps having compressive stress and interconnect structures containing same A dielectric capping layer having a dielectric constant of less than 4.2 is provided that exhibits a higher mechanical and electrical stability to UV and/or E-Beam radiation as compared to conventional dielectric capping layers. Also, the dielectric capping layer ma... | 01/29/2013 |
| 8053870 | Semiconductor structure incorporating multiple nitride layers to improve thermal dissipation away from a device and a method of forming the structure Disclosed are embodiments of a semiconductor structure that incorporates multiple nitride layers stacked between the center region of a device and a blanket oxide layer. These nitride layers are more thermally conductive than the blanket oxide layer and, thus provid... | 11/08/2011 |
| 7939915 | Contact etch stop film A system and method for improved dry etching system. According to an embodiment, the present invention provides a partially completed integrated circuit device. The partially completed integrated circuit device includes a semiconductor substrate having a surface reg... | 05/10/2011 |
| 7825497 | Method of manufacture of contact plug and interconnection layer of semiconductor device A method of manufacturing a semiconductor device including forming two first gate electrodes along a first direction on a first surface of a semiconductor substrate and source/drain areas sandwiching a channel region under each of the first gate electrodes, forming ... | 11/02/2010 |
| 7786552 | Semiconductor device having hydrogen-containing layer A method for reducing leakage current in a semiconductor structure is disclosed. One or more dielectric layers are formed on a semiconductor substrate, on which at least one device is constructed. A hydrogen-containing layer is formed over the dielectric layers. A s... | 08/31/2010 |
| 7646080 | Protective film structure A protective film structure (100) includes a base (110) and a resistive film (120) formed on a surface of the base. The base is comprised of amorphous boron nitride or amorphous boron carbide, and is formed on a surface of a substrate (10... | 01/12/2010 |
| 7629672 | Semiconductor devices and manufacturing method thereof A semiconductor device is provided with a semiconductor substrate having circuit elements formed therein, and an insulating protective film formed on the semiconductor substrate. Hydroxyl groups (OH) are attached to a surface of the protective film. As a result, the... | 12/08/2009 |
| 7629673 | Contact etch stop film A system and method for improved dry etching system. According to an embodiment, the present invention provides a partially completed integrated circuit device. The partially completed integrated circuit device includes a semiconductor substrate having a surface reg... | 12/08/2009 |
| 7566950 | Flexible pixel array substrate The present invention provides a method for fabricating a flexible pixel array substrate as follows. First, a release layer is formed on a rigid substrate. Next, on the release layer, a polymer film is formed, the adhesive strength between the rigid substrate and th... | 07/28/2009 |
| 7550822 | Dual-damascene metal wiring patterns for integrated circuit devices Methods of forming dual-damascene metal wiring patterns include forming a first metal wiring pattern (e.g., copper wiring pattern) on an integrated circuit substrate and forming an etch-stop layer on the first metal wiring pattern. These steps are followed by the st... | 06/23/2009 |
| 7402833 | Multilayer dielectric tunnel barrier used in magnetic tunnel junction devices, and its method of fabrication A multilayer dielectric tunnel barrier structure and a method for its formation which may be used in non-volatile magnetic memory elements comprises an ALD deposited first nitride junction layer formed from one or more nitride monolayers i.e., AlN, an ALD deposited ... | 07/22/2008 |
| 7402892 | Printed circuit board for connecting of multi-wire cabling to surge protectors A printed circuit board assembly for coupling a plurality of surge protectors to multi-line communication cables includes a multi-layer printed circuit board, to which has been mounted at least two cable connectors, having multiple female sockets for receiving stand... | 07/22/2008 |
| 7397073 | Barrier dielectric stack for seam protection The present invention provides a semiconducting device including a gate dielectric atop a semiconducting substrate, the semiconducting substrate containing source and drain regions adjacent the gate dielectric; a gate conductor atop the gate dielectric; a conformal ... | 07/08/2008 |
| 7391094 | Semiconductor structure and method of making same A semiconductor structure includes a substrate having a surface and being made of a material that provides atypical surface properties to the surface, a bonding layer on the surface of the substrate, and a further layer molecularly bonded to the bonding layer. A met... | 06/24/2008 |
| 7385276 | Semiconductor device, and method for manufacturing the same The invention is characterized by attaining a lower dielectric constant and including an inorganic dielectric film which is formed on the surface of a substrate and has a cyclic porous structure having a pore ratio of 50% or higher. ... | 06/10/2008 |
| 7368782 | Dual-bit non-volatile memory cell and method of making the same A non-volatile memory cell having a local silicon nitride layer to control dispersion of hot electrons is disclosed. The dual-bit non-volatile memory cell has a stack of layers including silicon on the surface of a substrate. The stack of layers has at least one fir... | 05/06/2008 |
| 7368804 | Method and apparatus of stress relief in semiconductor structures A method, apparatus and system are provided for relieving stress in the via structures of semiconductor structures whenever a linewidth below a via is larger than a ground-rule, including providing a via at least as large as the groundrule, providing a landing pad a... | 05/06/2008 |
| 7361974 | Manufacturing method for an integrated semiconductor structure The present invention provides a manufacturing method for an integrated semiconductor structure comprising the steps of: providing a semiconductor substrate having a plurality of gate stacks in a first region and at least one gate stack in a second region; forming a... | 04/22/2008 |
| 7358587 | Semiconductor structures In one aspect, the invention includes a method of forming a material within an opening, comprising: a) forming an etch-stop layer over a substrate, the etch-stop layer having an opening extending therethrough to expose a portion of the underlying substrate and compr... | 04/15/2008 |
| 7348277 | Methods of fabricating semiconductor device using sacrificial layer There are provided methods of fabricating a semiconductor device using a sacrificial layer. The methods provide an approach to maintaining thickness distribution of the interlayer insulating layers below a sacrificial layer uniform on an overall surface of a semicon... | 03/25/2008 |
| 7315076 | Display device and manufacturing method of the same A display device is provided in which contact holes, each having a sidewall with an ideal tapered shape, are formed in a structure in which a silicon oxide film, a silicon nitride film and a silicon oxide film are stacked in the named order. The display device inclu... | 01/01/2008 |
| 7312400 | Multilayer wiring board, base for multilayer wiring board, printed wiring board and its manufacturing method A multilayer wiring board assembly component comprises: an insulating substrate component (the insulating resin layer 111); a conductive layer 112 formed on one surface of said insulating substrate component 111 in the form of an electrode patte... | 12/25/2007 |
| 7300868 | Damascene interconnection having porous low k layer with a hard mask reduced in thickness A method is provided of fabricating a damascene interconnection. The method begins by forming on a substrate a first dielectric layer, a capping layer on the first dielectric sublayer and a resist pattern over the capping layer to define a first interconnect opening... | 11/27/2007 |
| 7294578 | Use of a plasma source to form a layer during the formation of a semiconductor device A method used to form a semiconductor device having a capacitor comprises placing a semiconductor wafer assembly into a chamber of a plasma source, the wafer assembly comprising a layer of insulation having at least one contact therein and a surface, and further com... | 11/13/2007 |
| 7285826 | High mobility CMOS circuits Semiconductor structure formed on a substrate and process of forming the semiconductor. The semiconductor includes a plurality of field effect transistors having a first portion of field effect transistors (FETS) and a second portion of field effect transistors. A f... | 10/23/2007 |
| 7282436 | Plasma treatment for silicon-based dielectrics An embodiment of the invention is a method of manufacturing a semiconductor wafer. The method includes depositing spin-on-glass material over the semiconductor wafer (step 208), modifying a top surface of the spin-on glass material to form a SiO2 l... | 10/16/2007 |
| 7273566 | Gas compositions Processes, etchants, and apparatus useful for etching an insulating oxide layer of a substrate without damaging underlying nitride features or field oxide regions. The processes exhibit good selectivity to both nitrides and field oxides. Integrated circuits produced... | 09/25/2007 |
| 7271463 | Trench insulation structures including an oxide liner that is thinner along the walls of the trench than along the base A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, a liner layer preferably is deposited into the trench. An anisotropic plasma process is then performed on the ... | 09/18/2007 |
| 7265437 | Low k dielectric CVD film formation process with in-situ imbedded nanolayers to improve mechanical properties A low k dielectric stack having an effective dielectric constant k, of about 3.0 or less, in which the mechanical properties of the stack are improved by introducing at least one nanolayer into the dielectric stack. The improvement in mechanical properties is achiev... | 09/04/2007 |
| 7262127 | Method for Cu metallization of highly reliable dual damascene structures The present invention provides a method for forming a void-free copper damascene structure comprising a substrate having a conductive structure, a first dielectric layer on the substrate, a diffusion barrier layer on the first dielectric layer, and a second dielectr... | 08/28/2007 |
| 7259432 | Semiconductor device for reducing parasitic capacitance produced in the vicinity of a transistor located within the semiconductor device A semiconductor device includes: a gate electrode formed on a substrate; impurity regions formed in the substrate and to both sides of the gate electrode; a first interlayer insulating film formed to cover the gate electrode; and a second interlayer insulating film ... | 08/21/2007 |
| 7256421 | Display device having a structure for preventing the deterioration of a light emitting device A structure for preventing deteriorations of a light-emitting device and retaining sufficient capacitor elements' (condenser) required by each pixel is provided. A first passivation film, a second metal layer, a flattening film, a barrier film, and a third metal lay... | 08/14/2007 |
| 7250364 | Semiconductor devices with composite etch stop layers and methods of fabrication thereof Semiconductor devices with composite etch stop layers and methods of fabrication thereof. An semiconductor device with a composite etch stop layer includes a substrate having a conductive member, a first etch stop layer on the substrate and the conductive member, a ... | 07/31/2007 |
| 7247903 | Semiconductor memory device A semiconductor memory device having a transistor formed on a semiconductor substrate and a capacitor formed on the upper layer of the transistor and electrically connected to the transistor, includes: a cell contact which is formed on a first interlayer insulation ... | 07/24/2007 |
| 7235493 | Low-k dielectric process for multilevel interconnection using mircocavity engineering during electric circuit manufacture One embodiment of a method for forming a low-k dielectric for a semiconductor device assembly comprises forming a silicon dioxide layer, then forming a patterned masking layer such as silicon nitride on the silicon dioxide. Using the patterned nitride layer as a pat... | 06/26/2007 |
| 7235490 | Method of manufacturing semiconductor device A method of manufacturing a semiconductor device comprises preparing a working film to be processed, forming an adhesion improving region on the working film for increasing an adhesion between the working film and a mask material containing carbon, forming the mask ... | 06/26/2007 |
| 7232748 | BARC/resist via etchback process A BARC or other sacrificial fill layer etch comprises a selective etch chemistry of Ar/O2/CO. The BARC etch may be used in a via-first dual damascene method. After via (116) pattern and etch, a BARC/sacrificial fill layer (120) is deposited ... | 06/19/2007 |
| 7227244 | Integrated low k dielectrics and etch stops A method of depositing and etching dielectric layers having low dielectric constants and etch rates that vary by at least 3:1 for formation of horizontal interconnects. The amount of carbon or hydrogen in the dielectric layer is varied by changes in deposition condi... | 06/05/2007 |
| 7217647 | Structure and method of making a semiconductor integrated circuit tolerant of mis-alignment of a metal contact pattern Disclosed is a method of fabricating a field effect transistor. In the method, a gate stack on a top surface of a semiconductor substrate is formed, and then a first spacer is formed on a sidewall of the gate stack. Next, a silicide self-aligned to the first spacer ... | 05/15/2007 |
| 7211485 | Method of fabricating flash memory device and flash memory device fabricated thereby There are provided a method of fabricating a flash memory device and a flash memory device fabricated thereby. The method of fabricating a flash memory device includes forming an isolation layer defining an active region in a semiconductor substrate, wherein the iso... | 05/01/2007 |
