Did You Know...
...that Robert Adler has the dubious distinction of being the Father of the Couch Potato? Back in 1955 Adler was employed by what was then Zenith Radio Corp., where he was charged to invent something that would allow viewers to turn down the TV volume without leaving their chairs. After a series of flops (such as a wired contraption that people tripped over), Adler hit on the idea of using sound waves. Thus the Remote Control was born...
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8183671 | Semiconductor device and method of manufacturing the same A semiconductor device includes a device isolation insulating film which is buried in a semiconductor substrate, a gate insulation film which is provided on the semiconductor substrate, a gate electrode which is provided on the gate insulation film, a source region ... | 05/22/2012 |
| 8169058 | Semiconductor device and method of stacking die on leadframe electrically connected by conductive pillars A semiconductor device has a first semiconductor die mounted to a first contact pad on a leadframe or substrate with bumps. A conductive pillar is formed over a second semiconductor die. The second die is mounted over the first die by electrically connecting the con... | 05/01/2012 |
| 8164166 | Interfacial roughness reducing film, wiring layer, semiconductor device, and method of manufacturing semiconductor device An interfacial roughness reducing film which is in contact, on one side thereof, with an insulating film and in contact, on a side opposite from the one side, with wiring comprises a Si—O bond, and is formed using a composition containing a silicon compound that c... | 04/24/2012 |
| 8154106 | Coating and developing system and coating and developing method A coating and developing system for forming a resist film on a substrate by coating the substrate with a liquid resist and developing the resist film after the resist film has been processed by immersion exposure that forms a liquid layer on the surface of the subst... | 04/10/2012 |
| 8138578 | Method and system for creating self-aligned twin wells with co-planar surfaces in a semiconductor device A method and system for providing a twin well in a semiconductor device is described. The method and system include providing at least one interference layer and providing a first mask that covers a first portion of the semiconductor device and uncovers a second por... | 03/20/2012 |
| 8093689 | Attachment member for semiconductor sensor device A semiconductor sensor device is electrically coupled to an object. An attachment member attaches the semiconductor sensor device to the object. The attachment member comprises a first conductive contact region and a second conductive contact region. An insulating p... | 01/10/2012 |
| 8035200 | Neutralization of trapped charge in a charge accumulation layer of a semiconductor structure A semiconductor structure. The semiconductor structure includes a semiconductor layer, a charge accumulation layer on top of the semiconductor layer, a doped region in direct physical contact with the semiconductor layer; and a device layer on and in direct physical... | 10/11/2011 |
| 7898065 | Structure and method for device-specific fill for improved anneal uniformity Disclosed are embodiments of a wafer that incorporates fill structures with varying configurations to provide uniform reflectance. Uniform reflectance is achieved by distributing across the wafer fill structures having different semiconductor materials such that app... | 03/01/2011 |
| 7692275 | Structure and method for device-specific fill for improved anneal uniformity Disclosed are embodiments of a wafer that incorporates fill structures with varying configurations to provide uniform reflectance. Uniform reflectance is achieved by distributing across the wafer fill structures having different semiconductor materials such that app... | 04/06/2010 |
| 7687890 | Controlling substrate surface properties via colloidal coatings Methods and apparatus to control surface properties via colloidal coatings are described. In one embodiment, colloidal coating may be used on a surface to enhance flow control. Other embodiments are also described. ... | 03/30/2010 |
| 7598595 | Fabrication of nanoporous antireflection film A nanoporous antireflection coating preparation method. A sol-gel precursor solution containing an organic template is coated onto a substrate. The sol-gel precursor solution containing the organic template is dried into a film. The organic template within the film ... | 10/06/2009 |
| 7564119 | Adhesive sheet for laser dicing and its manufacturing method An adhesive sheet for laser dicing is used for dicing a workpiece into individual chips by light absorption ablation of laser beam and has at least an adhesive layer on one side of a base material which has a surface opposite to the adhesive layer having no convex p... | 07/21/2009 |
| 7423330 | Semiconductor device with strain A semiconductor device includes: a semiconductor substrate having a p-MOS region; an element isolation region formed in a surface portion of the semiconductor substrate and defining p-MOS active regions in the p-MOS region; a p-MOS gate electrode structure formed ab... | 09/09/2008 |
| 7400031 | Asymmetrically stressed CMOS FinFET A CMOS device comprising a FinFET comprises at least one fin structure comprising a source region; a drain region; and a channel region comprising silicon separating the source region from the drain region. The FinFET further comprises a gate region comprising a N+ ... | 07/15/2008 |
| 7397126 | Semiconductor device The present invention provides inhibiting an electrical leakage caused by anion migration. A trenched portion 15 is provided as ion migration-preventing zone between a source electrode 4 and a gate electrode 5. The trenched portion 15 is ... | 07/08/2008 |
| 7364778 | Container for an electronic component A container for an electronic component made of a resin, wherein when the container and an electronic component contained in the container are rubbed 20,000 times, a static electrification voltage of at most 2,000V by the absolute value on the surface of the electro... | 04/29/2008 |
| 7357883 | Conductive adhesive, method of producing the same, and bonding method A conductive adhesive is formed by mixing a plurality of conductive fillers into a thermosetting resin. The conductive filler includes a core material made of copper-based metal, a coating film made of silver and a plurality of particles made of silver. The coating ... | 04/15/2008 |
| 7348610 | Multiple layer and crystal plane orientation semiconductor substrate A semiconductor on insulator substrate and a method of fabricating the substrate. The substrate including: a first crystalline semiconductor layer and a second crystalline semiconductor layer; and an insulating layer bonding a bottom surface of the first crystalline... | 03/25/2008 |
| 7345299 | Semiconductor device comprising a crystalline layer containing silicon/germanium, and comprising a silicon Enriched floating charge trapping media over the crystalline layer The invention includes non-volatile memory and logic devices associated with crystalline Si/Ge. The devices can include TFT constructions. The non-volatile devices include a floating gate or floating plate over the Si/Ge, and a pair of source/drain regions. The sour... | 03/18/2008 |
| 7339213 | Semiconductor device having a triple gate transistor and method for manufacturing the same In a semiconductor capable of reducing NBTI and a method for manufacturing the same, a multi-gate transistor includes an active region, gate dielectric, channels in the active region, and gate electrodes, and is formed on a semiconductor wafer. The active region has... | 03/04/2008 |
| 7335586 | Sealing porous dielectric material using plasma-induced surface polymerization A method for sealing a porous dielectric layer atop a substrate, wherein the dielectric layer is patterned to form at least a trench and at least a via, comprises applying a first plasma to a surface of the dielectric layer to silanolize the surface, treating the su... | 02/26/2008 |
| 7335969 | Method of monitoring introduction of interfacial species A method for monitoring a nitridation process, including: (a) providing a semiconductor substrate; (b) forming a first dielectric layer on a top surface of the substrate; (c) introducing a quantity of interfacial species into the substrate; (d) removing the first di... | 02/26/2008 |
| 7332796 | Devices and methods of preventing plasma charging damage in semiconductor devices Methods for protecting semiconductor devices from plasma charging damage are disclosed. An example disclosed method includes depositing an etching stop layer on a substrate with at least one predetermined structure; depositing a premetallic dielectric layer and a ch... | 02/19/2008 |
| 7333200 | Overlay metrology method and apparatus using more than one grating per measurement direction A method of controlling the lithography process used to fabricate patterns on layers of a semiconductor wafer is disclosed. The method includes providing at least two scatterometry targets, each target having a first pattern formed in an upper layer substantially al... | 02/19/2008 |
| 7317324 | Semiconductor integrated circuit testing device and method A plurality of resistors is connected to a plurality of output terminals of a semiconductor integrated circuit, respectively, and a predetermined voltage is applied to the plurality of resistors. Also, a predetermined operation pattern signal used to test functions ... | 01/08/2008 |
| 7301223 | High temperature electronic devices In at least some embodiments, electronic devices suitable for use at temperatures in excess of 200 C. may comprise an integrated circuit fabricated on a silicon carbide substrate, and a thick passivation layer. In other embodiments, electronic devices suitable for u... | 11/27/2007 |
| 7294871 | Top layers of metal for high performance IC's A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an ... | 11/13/2007 |
| 7294583 | Methods for the use of alkoxysilanol precursors for vapor deposition of SiOfilms A method for depositing conformal dielectric films uses alkoxy silanol or silanediol precursors and oxidizing and/or hydrolyzing agents. The method produces a material with liquid-like flow properties capable of achieving improved high aspect ratio gap fill more eff... | 11/13/2007 |
| 7288463 | Pulsed deposition layer gap fill with expansion material Conformal dielectric deposition processes supplemented with a deposited expansion material can fill high aspect ratio narrow width gaps with significantly reduced incidence of voids or weak spots. The technique can also be used generally to form composites, such as ... | 10/30/2007 |
| 7282375 | Wafer level package design that facilitates trimming and testing A wafer level method of packaging, trimming and testing integrated circuits is described. A wafer having trim pads is bumped before the wafer is trimmed. After the bumping, the dice on the wafer are trimmed and tested using standard trim probing and test probing tec... | 10/16/2007 |
| 7269062 | Gated diode nonvolatile memory cell A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of... | 09/11/2007 |
| 7253034 | Dual SIMOX hybrid orientation technology (HOT) substrates This invention provides a separation by implanted oxygen (SIMOX) method for forming planar hybrid orientation semiconductor-on-insulator (SOI) substrates having different crystal orientations, thereby making it possible for devices to be fabricated on crystal orient... | 08/07/2007 |
| 7253514 | Self-supporting connecting element for a semiconductor chip A connecting element for electrically connecting a semiconductor chip and a superordinate circuit board includes an elastic metal strip that is bent forming two metal limbs with flattened limb ends, thus forming a base between the metal limbs which is suitable for c... | 08/07/2007 |
| 7253483 | Semiconductor device layout and channeling implant process A device structure and method for forming graded junction using a implant process. Embodiments of the invention comprise implanting ions into said silicon substrate to form doped regions adjacent to said gate. The orientation of the channel region in the Si crystal ... | 08/07/2007 |
| 7247920 | Method of composite gate formation Methods for forming a nitride barrier film layer in semiconductor devices such as gate structures, and barrier layers, semiconductor devices and gate electrodes are provided. The nitride layer is particularly useful as a barrier to boron diffusion into an oxide film... | 07/24/2007 |
| 7241636 | Method and apparatus for providing structural support for interconnect pad while allowing signal conductance A method provides an interconnect structure having enhanced structural support when underlying functional metal layers are insulated with a low modulus dielectric. A first metal layer having a plurality of openings overlies the substrate. A first electrically insula... | 07/10/2007 |
| 7242063 | Symmetric non-intrusive and covert technique to render a transistor permanently non-operable A technique for and structures for camouflaging an integrated circuit structure. The technique including forming active areas of a first conductivity type and LDD regions of a second conductivity type resulting in a transistor that is always non-operational when sta... | 07/10/2007 |
| 7236244 | Alignment target to be measured with multiple polarization states An alignment target includes periodic patterns on two elements. The periodic patterns are aligned when the two elements are properly aligned. By measuring the two periodic patterns at multiple polarization states and comparing the resulting intensities of the polari... | 06/26/2007 |
| 7232739 | Multifunctional metallic bonding Methods are provided for producing a transfer layer of a semiconductor material on a final substrate. In some embodiments, the transfer layer is produced on the final substrate by forming a layer of semiconductor material on an initial support, assembling that layer... | 06/19/2007 |
| 7230705 | Alignment target with designed in offset An alignment target includes periodic patterns on two elements. The alignment target includes two locations, at least one of which has a designed in offset. In one embodiment, both measurement locations have a designed in offset of the same magnitude but opposite di... | 06/12/2007 |
