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| Number | Title | Issue Date |
| 8174095 | Semiconductor device and manufacturing method thereof A semiconductor device includes an insulator layer, and an n-channel MIS transistor having an n channel and a pMIS transistor having a p channel which are formed on the insulator layer, wherein the n channel of the n-channel MIS transistor is formed of an Si layer h... | 05/08/2012 |
| 8159051 | Semiconductor device and manufacturing method of semiconductor device In one aspect of the present invention, a semiconductor device may include a first semiconductor layer of a first conductivity type and having a main surface that has a first plane orientation, a second semiconductor layer of the first conductivity type and having a... | 04/17/2012 |
| 8067820 | Silocon wafer supporting method, heat treatment jig and heat-treated wafer Provided is a method applicable to the production of silicon wafers having crystal orientation or and consisting in specifying wafer-supporting positions on the occasion of heat treatment in a vertical heat treatment furnace as well as a heat treatment j... | 11/29/2011 |
| 8008751 | Semiconductor device and manufacturing method thereof A semiconductor device includes an insulator layer, and an n-channel MIS transistor having an n channel and a pMIS transistor having a p channel which are formed on the insulator layer, wherein the n channel of the n-channel MIS transistor is formed of an Si layer h... | 08/30/2011 |
| 7948061 | Group III nitride-based compound semiconductor device A characteristic feature of the invention is to form, in a Group III nitride-based compound semiconductor device, a negative electrode on a surface other than a Ga-polar C-plane. In a Group III nitride-based compound semiconductor light-emitting device, there are fo... | 05/24/2011 |
| 7915713 | Field effect transistors with channels oriented to different crystal planes An integrated circuit includes a first field effect transistor of a first carrier type and a second field effect transistor of a second, different carrier type. In a conductive state, a first channel of the first field effect transistor is oriented to one of a first... | 03/29/2011 |
| 7915714 | Semiconductor light emitting element and wafer There are provided a semiconductor light emitting element which allows an improvement in light extraction efficiency without increasing the number of fabrication steps, and a wafer. In a semiconductor light emitting element 1 formed by laminating a compound s... | 03/29/2011 |
| 7888780 | Semiconductor structures incorporating multiple crystallographic planes and methods for fabrication thereof A semiconductor structure includes a semiconductor mesa located upon an isolating substrate. The semiconductor mesa includes a first end that includes a first doped region separated from a second end that includes a second doped region by an isolating region interpo... | 02/15/2011 |
| 7884447 | Laser diode orientation on mis-cut substrates A microelectronic assembly in which a semiconductor device structure is directionally positioned on an off-axis substrate (201). In an illustrative implementation, a laser diode is oriented on a GaN substrate (201) wherein the GaN substrate includes a ... | 02/08/2011 |
| 7875960 | Hybrid oriented substrates and crystal imprinting methods for forming such hybrid oriented substrates A semiconductor structure with an insulating layer on a silicon substrate, a plurality of electrically-isolated silicon-on-insulator (SOI) regions separated from the substrate by the insulating layer, and a plurality of electrically-isolated silicon bulk regions ext... | 01/25/2011 |
| 7875959 | Semiconductor structure having selective silicide-induced stress and a method of producing same The channel of a MOSFET is selectively stressed by selectively stressing the silicide layers on the gate electrode and the source/drain. Stress in the silicide layer is selectively produced by orienting the larger dimensions of the silicide grains in a first directi... | 01/25/2011 |
| 7863712 | Hybrid orientation semiconductor structure with reduced boundary defects and method of forming same The present invention provides an improved amorphization/templated recrystallization (ATR) method for forming hybrid orientation substrates and semiconductor device structures. A direct-silicon-bonded (DSB) silicon layer having a (011) surface crystal orientation is... | 01/04/2011 |
| 7859086 | Nitride semiconductor single crystal substrate, and methods of fabricating the same and a vertical nitride semiconductor light emitting diode using the same A nitride semiconductor single crystal substrate, a manufacturing method thereof and a method for manufacturing a vertical nitride semiconductor device using the same. According to an aspect of the invention, in the nitride semiconductor single crystal substrate, up... | 12/28/2010 |
| 7834425 | Hybrid orientation SOI substrates, and method for forming the same The present invention relates to a hybrid orientation semiconductor-on-insulator (SOI) substrate structure that contains a base semiconductor substrate with one or more first device regions and one or more second device regions located over the base semiconductor su... | 11/16/2010 |
| 7808082 | Structure and method for dual surface orientations for CMOS transistors The present invention provides structures and methods for providing facets with different crystallographic orientations than what a semiconductor substrate normally provides. By masking a portion of a semiconductor surface and exposing the rest to an anisotripic etc... | 10/05/2010 |
| 7777306 | Defect-free hybrid orientation technology for semiconductor devices A semiconductor device includes a semiconductor material having two crystal orientations. The semiconductor material forms an active area of the device. A device channel is formed on the two crystal orientations, which include a first region formed in a first crysta... | 08/17/2010 |
| 7759772 | Method to form Si-containing SOI and underlying substrate with different orientations A method of forming a hybrid SOI substrate comprising an upper Si-containing layer and a lower Si-containing layer, wherein the upper Si-containing layer and the lower Si-containing layer have different crystallographic orientations. In accordance with the present i... | 07/20/2010 |
| 7755172 | Opto-electronic and electronic devices using N-face or M-plane GaN substrate prepared with ammonothermal growth A method for growing III-V nitride films having an N-face or M-plane using an ammonothermal growth technique. The method comprises using an autoclave, heating the autoclave, and introducing ammonia into the autoclave to produce smooth N-face or M-plane Gallium Nitri... | 07/13/2010 |
| 7737532 | Hybrid Schottky source-drain CMOS for high mobility and low barrier A CMOS device is provided. A semiconductor device comprises a substrate, the substrate having a first region and a second region, the first region having a first crystal orientation represented by a family of Miller indices comprising {i,j,k}, the second region havi... | 06/15/2010 |
| 7719089 | MOSFET having a channel region with enhanced flexure-induced stress A semiconductor device is provided that includes a semiconductor substrate, an n-channel MOSFET formed on the substrate and a p-channel MOSFET formed on the substrate. A first layer is formed to cover the n-channel MOSFET, wherein the first layer has a first flexure... | 05/18/2010 |
| 7667300 | Semiconductor device including gate stack formed on inclined surface and method of fabricating the same A semiconductor device includes a transistor. The transistor includes a substrate having an inclined surface, a first upper surface extending from a lower portion of the inclined surface, and a second upper surface extending from an upper end of the inclined surface... | 02/23/2010 |
| 7652353 | Semiconductor device A semiconductor device for improving performance of a p-channel transistor and an n-channel transistor having multi-finger structures. Gates of the n-channel transistor are arranged so that their gate width direction is parallel to one side of a first region. Gates ... | 01/26/2010 |
| 7649243 | Semiconductor structures incorporating multiple crystallographic planes and methods for fabrication thereof A semiconductor structure includes a semiconductor mesa located upon an isolating substrate. The semiconductor mesa includes a first end that includes a first doped region separated from a second end that includes a second doped region by an isolating region interpo... | 01/19/2010 |
| 7619300 | Super hybrid SOI CMOS devices The present invention provides semiconductor structures comprised of stressed channels on hybrid oriented. In particular, the semiconductor structures include a first active area having a first stressed semiconductor surface layer of a first crystallographic orienta... | 11/17/2009 |
| 7595544 | Semiconductor device and manufacturing method thereof An object of the present invention is to provide a semiconductor device and a manufacturing method thereof which can realize a normally-off field-effect transistor made of a III group nitride semiconductor. The present invention includes: placing a sapphire substrat... | 09/29/2009 |
| 7521776 | Soft error reduction of CMOS circuits on substrates with hybrid crystal orientation using buried recombination centers Novel semiconductor structures and methods are disclosed for forming a buried recombination layer underneath the bulk portion of a hybrid orientation technology by implanting at least one recombination center generating element to reduce single event upset rates in ... | 04/21/2009 |
| 7473985 | Hybrid oriented substrates and crystal imprinting methods for forming such hybrid oriented substrates A semiconductor structure with an insulating layer on a silicon substrate, a plurality of electrically-isolated silicon-on-insulator (SOI) regions separated from the substrate by the insulating layer, and a plurality of electrically-isolated silicon bulk regions ext... | 01/06/2009 |
| 7470973 | Semiconductor device and semiconductor integrated circuit device In each of a p-channel MOS transistor and an n-channel MOS transistor, a channel direction is set in the direction and a first stressor film accumulating therein a tensile stress is formed in a STI device isolation structure. Further, a second stressor film ac... | 12/30/2008 |
| 7449767 | Mixed orientation and mixed material semiconductor-on-insulator wafer The present disclosure relates, generally, to a semiconductor substrate with a planarized surface comprising mixed single-crystal orientation regions and/or mixed single-crystal semiconductor material regions, where each region is electrically isolated. In accordanc... | 11/11/2008 |
| 7439110 | Strained HOT (hybrid orientation technology) MOSFETs A strained HOT MOSFET fabrication method. The MOSFET fabrication method includes providing a semiconductor structure which includes (a) a first semiconductor layer having a first crystallographic orientation, (b) a buried insulating layer on top of the first semicon... | 10/21/2008 |
| 7432570 | Semiconductor device and manufacturing method thereof A semiconductor device includes a substrate, a p-channel MIS transistor formed on an n-type well on the substrate, having a first gate dielectric and a first gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111... | 10/07/2008 |
| 7423303 | Strained silicon directly-on-insulator substrate with hybrid crystalline orientation and different stress levels The present invention provides a strained Si directly on insulator (SSDOI) substrate having multiple crystallographic orientations and a method of forming thereof. Broadly, but in specific terms, the inventive SSDOI substrate includes a substrate; an insulating laye... | 09/09/2008 |
| 7420261 | Bulk nitride mono-crystal including substrate for epitaxy The invention relates to a substrate for epitaxy, especially for preparation of nitride semiconductor layers. Invention covers a bulk nitride mono-crystal characterized in that it is a mono-crystal of gallium nitride and its cross-section in a plane perpendicular to... | 09/02/2008 |
| 7414313 | Polymeric conductor donor and transfer method The present invention relates to a donor laminate for transfer of a conductive layer comprising at least one electronically conductive polymer on to a receiver, wherein the receiver is a component of a device. The present invention also relates to methods pertinent ... | 08/19/2008 |
| 7411273 | Nitride semiconductor substrate In an independent GaN film manufactured by creating a GaN layer on a base heterosubstrate using vapor-phase deposition and then removing the base substrate, owing to layer-base discrepancy in thermal expansion coefficient and lattice constant, bow will be a large ±... | 08/12/2008 |
| 7411274 | Silicon semiconductor substrate and its manufacturing method The present invention has been made in order to manufacture a silicon semiconductor substrate used for a semiconductor integrated circuit device, higher in carrier mobility, especially in electron mobility, which is a carrier of an n-type FET, on a {100} plane as a ... | 08/12/2008 |
| 7405436 | Stressed field effect transistors on hybrid orientation substrate A semiconductor structure having improved carrier mobility is provided. The semiconductor structures includes a hybrid oriented semiconductor substrate having at least two planar surfaces of different crystallographic orientation, and at least one CMOS device locate... | 07/29/2008 |
| 7400030 | Schottky diode with silver layer contacting the ZnO and MgZnO films In the present invention, there is provided semiconductor devices such as a Schottky UV photodetector fabricated on n-type ZnO and MgxZn1-xO epitaxial films. The ZnO and MgxZn1-xO films are grown on R-plane sapphire substr... | 07/15/2008 |
| 7396407 | Trench-edge-defect-free recrystallization by edge-angle-optimized solid phase epitaxy: method and applications to hybrid orientation substrates The present invention discloses the use of edge-angle-optimized solid phase epitaxy for forming hybrid orientation substrates comprising changed-orientation Si device regions free of the trench-edge defects typically seen when trench-isolated regions of Si are recry... | 07/08/2008 |
| 7388278 | High performance field effect transistors on SOI substrate with stress-inducing material as buried insulator and methods The present invention provides a semiconductor structure that includes a high performance field effect transistor (FET) on a semiconductor-on-insulator (SOI) in which the insulator thereof is a stress-inducing material of a preselected geometry. Such a structure ach... | 06/17/2008 |
