Bizarre Patents
A kissing shield comprised of a thin, flexible membrane and a frame or holder.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8169057 | Positive-intrinsic-negative (PIN)/negative-intrinsic-positive (NIP) diode A positive-intrinsic-negative (PIN)/negative-intrinsic-positive (NIP) diode includes a semiconductor substrate having first and second main surfaces opposite to each other. The semiconductor substrate is of a first conductivity. The PIN/NIP diode includes at least o... | 05/01/2012 |
| 8106485 | Chemical oxide removal of plasma damaged SiCOH low k dielectrics A structure and method for removing damages of a dual damascene structure after plasma etching. The method includes the use of sublimation processes to deposit reactive material onto the damaged regions and conditions to achieve a controlled removal of the damaged r... | 01/31/2012 |
| 8018032 | Silicon substrate and chip package structure with silicon base having stepped recess for accommodating chip A semiconductor process is provided. First, a silicon base is provided. Next, a surface of the silicon base is partially exposed and at least a stair structure is formed on the silicon base by etching the surface of the silicon base. The stair structure has a first ... | 09/13/2011 |
| 7994614 | Semiconductor wafer, semiconductor device, and method of manufacturing semiconductor device Provided is a semiconductor wafer with a scribe line region and a plurality of element forming regions partitioned by the scribe line region, the semiconductor wafer including: conductive patterns formed in the scribe line region; and an island-shaped passivation fi... | 08/09/2011 |
| 7928535 | Semiconductor device and semiconductor package having the same A semiconductor device having no voids and a semiconductor package using the same is described. The semiconductor device includes a semiconductor chip having a circuit section which is formed in a first area and a peripheral section which is formed in a second area ... | 04/19/2011 |
| 7902639 | Printable electric circuits, electronic components and method of forming the same Improved methods and articles providing conformal coatings for a variety of devices including electronic, semiconductor, and liquid crystal display devices. Peptide formulations which bind to nanoparticles and substrates, including substrates with trenches and vias,... | 03/08/2011 |
| 7855437 | Semiconductor device and semiconductor package having the same A semiconductor device having no voids and a semiconductor package using the same is described. The semiconductor device includes a semiconductor chip having a circuit section which is formed in a first area and a peripheral section which is formed in a second area ... | 12/21/2010 |
| 7843041 | Thin-film circuit device having a low strength region, method for manufacturing the thin-film circuit device, and electronic apparatus A thin-film circuit device includes a substrate and a thin-film circuit layer, disposed on the substrate, having an element region and a low-strength region. The element region includes thin-film elements. The low-strength region extends between an end portion of th... | 11/30/2010 |
| 7829977 | Low temperature co-fired ceramics substrate and semiconductor package A low-temperature co-fired ceramics (LTCC) substrate includes a plurality of substrate units and at least one cutting pattern. The cutting pattern is disposed between neighboring two of the substrate units. A semiconductor package including the LTCC substrate is als... | 11/09/2010 |
| 7825496 | Semiconductor device having a filling pattern around a storage structure and method of forming the same A semiconductor device includes an interlayer insulating layer on a semiconductor substrate, at least one plug on the semiconductor substrate, the plug extending through the interlayer insulating layer toward an upper portion of the semiconductor substrate, the plug... | 11/02/2010 |
| 7825495 | Semiconductor chip structure, method of manufacturing the semiconductor chip structure, semiconductor chip package, and method of manufacturing the semiconductor chip package A semiconductor chip structure may include a semiconductor chip, a first insulation layer and a redistribution layer. The first insulation layer may be formed on the semiconductor chip. The first insulation layer may have at least one first groove formed at an upper... | 11/02/2010 |
| 7768102 | Semiconductor device A semiconductor device comprises a semiconductor chip having a rear surface provided with an uneven structure having a preselected pattern and comprised of concave and convex portions. The preselected pattern of the uneven structure is tilted so as to be in parallel... | 08/03/2010 |
| 7755170 | Semiconductor device and semiconductor package having the same A semiconductor device having no voids and a semiconductor package using the same is described. The semiconductor device includes a semiconductor chip having a circuit section which is formed in a first area and a peripheral section which is formed in a second area ... | 07/13/2010 |
| 7696609 | Semiconductor device comprising a memory portion and a peripheral circuit portion The present invention provides a semiconductor chip that provides a semiconductor device with high reliability and low leak current, and a method of manufacturing such a semiconductor chip, and more specifically, provides a semiconductor chip comprising memory porti... | 04/13/2010 |
| 7652352 | Active structure of a semiconductor device An active structure of a semiconductor device. In one aspect, the active structure of the semiconductor device includes first to (n)th field regions, and first to (n+1)th active regions formed alternately with the first to (n)th fiel... | 01/26/2010 |
| 7638858 | Semiconductor device and manufacturing method thereof A semiconductor device includes: a substrate having a main surface, a rear surface and four side surfaces; a semiconductor element formed on the main surface of the substrate; a notch formed in at least one bottom part of the side surfaces of the substrate; and a cu... | 12/29/2009 |
| 7629671 | Semiconductor device having a resin protrusion with a depression and method manufacturing the same A semiconductor device including a semiconductor substrate having a plurality of electrodes, a resin protrusion formed on the semiconductor substrate, and an interconnect electrically connected to the electrodes and formed to extend over the resin protrusion. A depr... | 12/08/2009 |
| 7608911 | Semiconductor device package having a semiconductor element with a roughened surface A semiconductor device is disclosed, which comprises a semiconductor element in which a laminated film composed of a plurality of layers including an insulating film is formed on a surface of a semiconductor substrate, and a portion of the laminated film is removed ... | 10/27/2009 |
| 7605449 | Enhanced segmented channel MOS transistor with high-permittivity dielectric isolation material By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-powe... | 10/20/2009 |
| 7595543 | Semiconductor processing method for increasing usable surface area of a semiconductor wafer The invention provides a method for increasing the usable surface area of a semiconductor wafer having a substantially planar surface and a thickness dimension at right angles to said substantially planar surface, the method including the steps of selecting a strip ... | 09/29/2009 |
| 7582950 | Semiconductor chip having gettering layer, and method for manufacturing the same In a semiconductor chip A wherein an element layer 2 having transistors and the like is formed on the front face, and the back face is joined to an underlying member, such as a package substrate, the thickness T is made 100 μm or less, and thereafter, a gett... | 09/01/2009 |
| 7554177 | Attachment system incorporating a recess in a structure An attachment system. The attachment system includes a first structure and a second structure. The first structure has a surface and a recess in the surface. The second structure is molded into the recess and extends above the surface. The second structure adheres t... | 06/30/2009 |
| 7528465 | Integrated circuit on corrugated substrate By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-powe... | 05/05/2009 |
| 7468545 | Post passivation structure for a semiconductor device and packaging process for same A post passivation rerouting support structure comprises a relatively thin support layer above the passivation layer to support the RDL, and a relatively thick support layer for fine pitch interconnects extending from the RDL and terminating as contact structures at... | 12/23/2008 |
| 7449766 | Methods of forming a contact opening in a semiconductor assembly using a disposable hard mask Methods to form contact openings and allow the formation of self-aligned contacts for use in the manufacture of semiconductor devices are described. During formation of a multi-layered resist, a hard mask material is introduced beneath an anti-reflective coating to ... | 11/11/2008 |
| 7439578 | Semiconductor device A semiconductor device includes a trench formed in a surface of a semiconductor substrate. A conductor is embedded in the trench. A conductive layer is arranged adjacent to the trench on the surface of the semiconductor substrate. Semiconductor elements, which inclu... | 10/21/2008 |
| 7436035 | Method of fabricating a field effect transistor structure with abrupt source/drain junctions Microelectronic structures embodying the present invention include a field effect transistor (FET) having highly conductive source/drain extensions. Formation of such highly conductive source/drain extensions includes forming a passivated recess which is back filled... | 10/14/2008 |
| 7436009 | Via structures and trench structures and dual damascene structures Via hole and trench structures and fabrication methods are disclosed. The structure includes a conductive layer in a dielectric layer, and a via structure in the dielectric layer contacting a portion of a surface of the conductive layer. The via structure includes t... | 10/14/2008 |
| 7432148 | Shallow trench isolation by atomic-level silicon reconstruction Methods of forming an improved shallow trench isolation (STI) region are disclosed. Several exemplary techniques are proposed for treating STI sidewalls to improve the silicon (Si) surface at the atomic level. Each of the exemplary methods creates a smooth STI sidew... | 10/07/2008 |
| 7429752 | Method and structure for forming strained SI for CMOS devices A semiconductor device includes a semiconductor substrate having at least one gap, extending under a portion of the semiconductor substrate. A gate stack is on the semiconductor substrate. A strain layer is formed in at least a portion of the at least one gap. The s... | 09/30/2008 |
| 7411269 | Isolation structure configurations for modifying stresses in semiconductor devices An apparatus and methods for modifying isolation structure configurations for MOS devices to either induce or reduce tensile and/or compressive stresses on an active area of the MOS devices. The isolation structure configurations according to the present invention i... | 08/12/2008 |
| 7405138 | Manufacturing method of stack-type semiconductor device A semiconductor device capable mounting semiconductor elements having different functions without increasing the area of the semiconductor device, and its manufacturing method are presented. A part if wiring 104 is formed al so at the side surface of a semico... | 07/29/2008 |
| 7402867 | Semiconductor device In a semiconductor device, a plurality of first diffusion regions of a first conductive type are formed on a diffusion layer well of the first conductive type. A plurality of second diffusion regions of a second conductive type are formed on the diffusion layer well... | 07/22/2008 |
| 7397126 | Semiconductor device The present invention provides inhibiting an electrical leakage caused by anion migration. A trenched portion 15 is provided as ion migration-preventing zone between a source electrode 4 and a gate electrode 5. The trenched portion 15 is ... | 07/08/2008 |
| 7391087 | MOS transistor structure and method of fabrication An MOS device comprising a gate dielectric formed on a first conductivity type region. A gate electrode formed on the gate dielectric. A pair of sidewall spacers are formed along laterally opposite sidewalls of the gate electrode. A pair of deposited silicon or sili... | 06/24/2008 |
| 7387951 | Method of dicing semiconductor wafer into chips, and apparatus using this method The invention relates to a semiconductor wafer dicing method of dicing a semiconductor wafer along parting lines into chips. The semiconductor wafer in which parting lines along which the semiconductor wafer is diced into chips are formed is held by an adhesive tape... | 06/17/2008 |
| 7378744 | Plasma treatment at film layer to reduce sheet resistance and to improve via contact resistance A method of manufacturing a semiconductor device contact including forming an insulating layer over a substrate and forming an agglutinating layer over the insulating layer. The agglutinating layer is then exposed to a plasma treatment. A barrier layer is formed ove... | 05/27/2008 |
| 7368385 | Method for producing a structure on the surface of a substrate The present invention relates to a method for producing a structure serving as an etching mask on the surface of a substrate. In this case, a first method involves forming a first partial structure on the surface of the substrate, which has structure elements that a... | 05/06/2008 |
| 7365413 | Reduced power distribution mesh resistance using a modified swiss-cheese slotting pattern Electrical interconnects with a slotting pattern are provided in the present invention. In addition, the masks for making such interconnects and semiconductor devices incorporating such interconnects are also provided in the present invention. The slotting pattern m... | 04/29/2008 |
| 7365437 | Method of wet etching vias and articles formed thereby A method for forming smooth walled, prismatically-profiled through-wafer vias and articles formed through the method. An etch stop material is provided on a wafer, which may be a silicon wafer. A mask material is provided on the etch stop material and patterne... | 04/29/2008 |
