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| Number | Title | Issue Date |
| 8188574 | Pedestal guard ring having continuous M1 metal barrier connected to crack stop A microelectronic element, e.g., a semiconductor chip having a silicon-on-insulator layer (“SOI layer”) separated from a bulk monocrystalline silicon layer by a buried oxide (BOX) layer in which a crack stop extends in first lateral directions at least generally... | 05/29/2012 |
| 8049308 | Bond pad for low K dielectric materials and method for manufacture for semiconductor devices A semiconductor device having an improved contact structure. The device has a semiconductor substrate and a plurality of gate structures formed on the substrate. The device has a first interlayer dielectric overlying the gate structures. The device has a first coppe... | 11/01/2011 |
| 7919832 | Stack resistor structure for integrated circuits A resistor structure for an integrated circuit includes a first set of contacts connected between a semiconductor layer and a first conductive layer; and a second set of plugs connected between the first conductive layer and a second conductive layer, wherein the fi... | 04/05/2011 |
| 7737531 | Wafer including a reinforcing flange formed upright at a periphery and method for manufacturing the same A wafer with an orientation notch being cut in a portion of its circumference, the wafer includes: a reinforcing flange formed upright at periphery; and a thin section surrounded by the reinforcing flange and having a smaller thickness than the reinforcing flange. T... | 06/15/2010 |
| 7705430 | Semiconductor wafer and processing method for same A semiconductor wafer which is generally circular, and which has on its face an annular surplus region present in an outer peripheral edge portion of the face, and a circular device region surrounded by the surplus region, the device region having many semiconductor... | 04/27/2010 |
| 7675142 | Electromechanical non-volatile memory devices Electromechanical non-volatile memory devices are provided including a semiconductor substrate having an upper surface including insulation characteristics. A first electrode pattern is provided on the semiconductor substrate. The first electrode pattern exposes por... | 03/09/2010 |
| 7560800 | Die seal with reduced noise coupling A die seal structure for sealing integrated circuit devices formed on a semiconductor substrate. The die seal structure includes a die seal and a junction diode. The die seal only connects to the semiconductor substrate through the junction diode, thereby reducing n... | 07/14/2009 |
| 7427801 | Integrated circuit transformer devices for on-chip millimeter-wave applications Methods are provided for building integrated circuit transformer devices having compact and optimized architectures for use in MMW (millimeter-wave) applications. The integrated circuit transformer devices have universal and scalable architectures that can be used a... | 09/23/2008 |
| 7413920 | Double-sided etching method using embedded alignment mark A double-sided etching method using an embedded alignment mark includes: preparing a substrate having first and second alignment marks embedded in an intermediate portion thereof; etching an upper portion of the substrate so as to expose the first alignment mark fro... | 08/19/2008 |
| 7402856 | Non-planar microelectronic device having isolation element to mitigate fringe effects and method to fabricate same A non-planar microelectronic device, a method of fabricating the device, and a system including the device. The non-planar microelectronic device comprises: a substrate body including a substrate base and a fin, the fin defining a device portion at a top region ther... | 07/22/2008 |
| 7368803 | System and method for protecting microelectromechanical systems array using back-plate with non-flat portion Disclosed is an electronic device utilizing interferometric modulation and a package of the device. The packaged device includes a substrate, an interferometric modulation display array formed on the substrate, and a back-plate. The back-plate is placed over the dis... | 05/06/2008 |
| 7360307 | Techniques for manufacturing a circuit board with an improved layout for decoupling capacitors A circuit board module has an IC device, discrete components, and a circuit board structure in electrical communication with the IC device and the discrete component. The circuit board structure includes non-conductive material defining a top surface of the circuit ... | 04/22/2008 |
| 7358593 | Microfabricated miniature grids A grid structure and method for manufacturing the same. The grid is used for gating a stream of charged particles in certain types of particle measurement instruments, such as ion mobility spectrometers and the like. The methods include various microfabrication tech... | 04/15/2008 |
| 7352054 | Semiconductor device having conducting portion of upper and lower conductive layers A semiconductor device includes a base plate, at least one first conductive layer carried by the base plate, and a semiconductor constructing body formed on or above the base plate, and having a semiconductor substrate and a plurality of external connecting electrod... | 04/01/2008 |
| 7352040 | Microelectromechanical systems having trench isolated contacts, and methods for fabricating same There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a MEMS device, and technique of fabricating or manufacturing a MEMS device, having mechanical structures encapsulated in a chamber prior to final packagin... | 04/01/2008 |
| 7342320 | Electronic component with semiconductor chips, electronic assembly composed of stacked semiconductor chips, and methods for producing an electronic component and an electronic assembly An electronic component includes a semiconductor chip with an active front face and a passive rear face, with contact connections and contact surfaces respectively being provided on the active front face and/or on the passive rear face, and with conductive connectio... | 03/11/2008 |
| 7326960 | Semiconductor circuit constructions The invention includes a method of forming semiconductor circuitry wherein a first semiconductor structure comprising a first monocrystalline semiconductor substrate is bonded to a second semiconductor structure comprising a second monocrystalline semiconductor subs... | 02/05/2008 |
| 7309623 | Method of fabricating a stacked die in die BGA package Semiconductor devices and stacked die assemblies, and methods of fabricating the devices and assemblies for increasing semiconductor device density are provided. ... | 12/18/2007 |
| 7302982 | Label applicator and system A label applicator including a support surface having a central area and curving downwardly from the central area. A post assembly extends up from the central area such that a label having a label through-hole can be positioned in a support position generally on the... | 12/04/2007 |
| 7303976 | Wafer bonding method One embodiment of a micro-electronic device includes a substrate including micro-electronic components thereon, and a cover including a ring of sealing material secured to the substrate and a raised ring of material positioned opposite the cover from the ring of sea... | 12/04/2007 |
| 7282392 | Method of fabricating a stacked die in die BGA package Semiconductor devices and stacked die assemblies, and methods of fabricating the devices and assemblies for increasing semiconductor device density are provided. ... | 10/16/2007 |
| 7279774 | Bulk substrates in FinFETs with trench insulation surrounding FIN pairs having FINs separated by recess hole shallower than trench A finFET device includes a semiconductor substrate having specific regions surrounded with a trench. The trench is filled with an insulating layer, and recess holes are formed within the specific regions such that channel fins are formed by raised portions of the se... | 10/09/2007 |
| 7247947 | Semiconductor device comprising a plurality of semiconductor constructs A semiconductor device includes a first semiconductor construct provided on a base plate and having a semiconductor substrate and external connection electrodes. An insulating layer is provided on the base plate around the first semiconductor construct. An upper lay... | 07/24/2007 |
| 7242012 | Lithography device for semiconductor circuit pattern generator General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor ... | 07/10/2007 |
| 7230274 | Reduction of carrot defects in silicon carbide epitaxy Single crystal silicon carbide epitaxial layer on an off-axis substrate are manufactured by placing the substrate in an epitaxial growth reactor, growing a first layer of epitaxial silicon carbide on the substrate, interrupting the growth of the first layer of epita... | 06/12/2007 |
| 7227243 | Semiconductor device An object of the present invention is to provide a semiconductor device capable of adapting to an increase in the external terminals which can be arranged on the mount surface (a greater number of pins). A mesa-type semiconductor chip is mounted on a mount surface o... | 06/05/2007 |
| 7223696 | Methods for maskless lithography General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor ... | 05/29/2007 |
| 7214995 | Mechanism to prevent actuation charging in microelectromechanical actuators According to one embodiment a microelectromechanical (MEMS) switch is disclosed. The MEMS switch includes a top movable electrode, and an actutaion electrode with an undoped polysilicon stopper region to contact the top movable electrode when an actuation current is... | 05/08/2007 |
| 7208794 | High-density NROM-FINFET Semiconductor memory having memory cells, each including first and second conductively-doped contact regions and a channel region arranged between the latter, formed in a web-like rib made of semiconductor material and arranged one behind the other in this sequence ... | 04/24/2007 |
| 7193239 | Three dimensional structure integrated circuit A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, red... | 03/20/2007 |
| 7193295 | Process and apparatus for thinning a semiconductor workpiece The present invention provides system and apparatus for use in processing wafers. The new system and apparatus allows for the production of thinner wafers that at same time remain strong. As a result, the wafers produced by the present process are less susceptible t... | 03/20/2007 |
| 7176452 | Microfabricated beam modulation device A beam modulation device gate is constructed from a silicon material, such as a silicon layer on an silicon on insulator wafer. The device further comprises a set of electrical contacts on the layer. The layer defines a set of electrically conducting silicon materia... | 02/13/2007 |
| 7176545 | Apparatus and methods for maskless pattern generation General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor ... | 02/13/2007 |
| 7176555 | Flip chip package with reduced thermal stress A flip-chip package includes a packaging substrate; an integrated circuit die affixed to the packaging substrate, wherein the integrated circuit die includes an active integrated circuit surrounded by a peripheral die seal ring therein; and a thermal stress releasin... | 02/13/2007 |
| 7170126 | Structure of vertical strained silicon devices A trench capacitor vertical-transistor DRAM cell in a SiGe wafer compensates for overhang of the pad nitride by forming an epitaxial strained silicon layer on the trench walls that improves transistor mobility, removes voids from the poly trench fill and reduces res... | 01/30/2007 |
| 7138295 | Method of information processing using three dimensional integrated circuits A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, red... | 11/21/2006 |
| 7138672 | Apparatus and method for making a tensile diaphragm with an insert An apparatus and method for making a tensile diaphragm with an insert region of a material dissimilar to the diaphragm, the insert region being suitable for the fabrication of a nanopore. ... | 11/21/2006 |
| 7132737 | Package for electronic component and method of manufacturing piezoelectric device Aspects of the invention provide a package for accommodating a piezoelectric resonator that can include more mounting electrodes than connecting electrodes of the piezoelectric resonator element. The mounting electrodes can be electrically connected with a wiring pa... | 11/07/2006 |
| 7129566 | Scribe street structure for backend interconnect semiconductor wafer integration A method of making a semiconductor device includes forming a wafer having a substrate and an interconnect structure over the substrate. The wafer also includes a plurality of die areas and a street located between a first die area of the plurality and a second die a... | 10/31/2006 |
| 7129565 | Semiconductor device, method of manufacturing the same, and phase shift mask A main wall part is provided so as to surround an integrated circuit part. A sub-wall part which is in “L” shape is provided between each corner of the main wall part and the integrated circuit part. Therefore, even if the stress is concentrated due to heat trea... | 10/31/2006 |
