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Dionysius Lardner, Professor of Natural Philosophy and Astronomy at University College, London ; 1830
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| Number | Title | Issue Date |
| 8183669 | Nitride semiconductor wafer having a chamfered edge A nitride semiconductor wafer is planar-processed by grinding a bottom surface of the wafer, etching the bottom surface by, e.g., KOH for removing a bottom process-induced degradation layer, chamfering by a rubber whetstone bonded with 100 wt %-60 wt % #3000-#600 di... | 05/22/2012 |
| 8143703 | Methods and devices for forming nanostructure monolayers and devices including such monolayers Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, patterning using resist, and/or use of devices that facilitate array formation. Related devices for ... | 03/27/2012 |
| 8129822 | Template for three-dimensional thin-film solar cell manufacturing and methods of use A template 100 for three-dimensional thin-film solar cell substrate formation for use in three-dimensional thin-film solar cells. The template 100 comprises a substrate which comprises a plurality of posts 102 and a plurality of trenches 104 | 03/06/2012 |
| 8110898 | Polymer-embedded semiconductor rod arrays A structure consisting of well-ordered semiconductor structures embedded in a binder material which maintains the ordering and orientation of the semiconductor structures. Methods for forming such a structure include forming the semiconductor structures on a substra... | 02/07/2012 |
| 8093687 | Methods for forming an assembly for transfer of a useful layer using a peripheral recess area to facilitate transfer Methods for transferring of a useful layer from a support are described. In an embodiment, the method includes for facilitating transfer of a useful layer from a support by providing an interface in a first support to define a useful layer; and forming a peripheral ... | 01/10/2012 |
| 8084845 | Subresolution silicon features and methods for forming the same Novel etch techniques are provided for shaping silicon features below the photolithographic resolution limits. FinFET devices are defined by recessing oxide and exposing a silicon protrusion to an isotropic etch, at least in the channel region. In one implementation... | 12/27/2011 |
| 8082537 | Method and apparatus for implementing spatially programmable through die vias in an integrated circuit Examples of the invention relate to a method, apparatus, and computer readable medium for designing a mother integrated circuit (IC) configured for stacking with at least one daughter IC. A layout of the mother IC includes at least one interface tile having an elect... | 12/20/2011 |
| 8072044 | Semiconductor die containing lateral edge shapes and textures Methods for singulating a semiconductor wafer into a plurality of individual dies that contain lateral edges or sidewalls and the semiconductor dies formed from these methods are described. The dies are formed from methods that use a front to back photolithography a... | 12/06/2011 |
| 8072045 | Extendable connector and network Extendable connectors are facilitated. According to an example embodiment, an integrated electrical circuit uses a connector that has first and second connected ends. The connector is unbundled from an initial state in which the first and second connected ends are s... | 12/06/2011 |
| 8067818 | Nonplanar device with thinned lower body portion and method of fabrication A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distan... | 11/29/2011 |
| 8058706 | Delamination resistant packaged die having support and shaped die having protruding lip on support A packaged electronic device includes a thickness shaped IC die including a top portion, top surface, active circuitry, bottom portion and bottom surface. A cross sectional area of the bottom surface is ≧5% less than a cross sectional area of the top surface to pr... | 11/15/2011 |
| 8039927 | Linear semiconductor substrate, and device, device array and module, using the same The linear semiconductor substrate 1 or 2 of the present invention comprises at least one desired thin film 4 formed on a linear substrate 3 having a length ten or more times greater than a width, thickness, or diameter of the linear subs... | 10/18/2011 |
| 8013424 | Semiconductor device and method of fabricating the same A semiconductor device according to an embodiment includes: a semiconductor substrate; a gate electrode formed on the semiconductor substrate via a gate insulating film; a channel region formed in a region of the semiconductor substrate below the gate electrode; an ... | 09/06/2011 |
| 7999353 | Mesoscale pyramids, hole arrays and methods of preparation Composite films comprising two-dimensional hole arrays, and related methods of preparing hole arrays. ... | 08/16/2011 |
| 7986029 | Dual SOI structure A semiconductor structure having a hybrid crystal orientation is provided. The semiconductor structure includes an insulator layer, e.g., a buried oxide (BOX), on a first semiconductor layer, and a second semiconductor layer on the buried oxide, wherein the first an... | 07/26/2011 |
| 7986030 | Nitride semiconductor substrate A nitride semiconductor substrate has a first surface forming a principal surface of the substrate. A first edge is formed by beveling at least a portion of an edge of the first surface of the substrate. A scattering region is formed in at least a portion of the fir... | 07/26/2011 |
| 7956441 | Method of increasing the area of a useful layer of material transferred onto a support A composite structure that includes front faces of the first and second substrates that are molecularly bonded to each other. The dimensions of the second substrate outline are larger than the first substrate outline, and a peripheral side of the second substrate su... | 06/07/2011 |
| 7952167 | Scribe line layout design A scribe line layout design to reduce the damage caused by sawing the wafer is presented. An embodiment comprises metal plates located within the scribe lines and at least partially within the junctions of the scribe lines. Each of these metal plates has one or more... | 05/31/2011 |
| 7944025 | Semiconductor constructions The invention includes a process whereby a solvent is utilized to remove soluble portions of a resist, and subsequently the solvent can be removed with a gas-fortified liquid. In particular aspects, the gas-fortified liquid emits bubbles during the removal of the so... | 05/17/2011 |
| 7902637 | Nano structure and method of manufacturing nano structure A nano structure formed on the surface of a substrate containing Si and having a pattern of at least 2 μm in depth, in which Ga or In is contained in the surface of the pattern, and the Ga or the In has a concentration distribution that an elemental composition rat... | 03/08/2011 |
| 7884446 | Femtosecond laser-induced formation of submicrometer spikes on a semiconductor substrate The present invention generally provides semiconductor substrates having submicron-sized surface features generated by irradiating the surface with ultra short laser pulses. In one aspect, a method of processing a semiconductor substrate is disclosed that includes p... | 02/08/2011 |
| 7884445 | Semiconductor device in wafer assembly An apparatus and method for holding a semiconductor device in a wafer. A bar is connected to the wafer. A first sidewall comprises a first end and a second, and is connected to the bar at its first end. A first tab comprises a first end and a second end, and is conn... | 02/08/2011 |
| 7872331 | Nitride semiconductor wafer A nitride semiconductor wafer is planar-processed by grinding a bottom surface of the wafer, etching the bottom surface by, e.g., KOH for removing a bottom process-induced degradation layer, chamfering by a rubber whetstone bonded with 100 wt %-60 wt % #3000-#600 di... | 01/18/2011 |
| 7868426 | Method of fabricating monolithic nanoscale probes A monolithic pair of nanoscale probes, including: a substrate having a cavity that extends from a surface of the substrate into its body; a dielectric layer formed on the substrate; a pair of nanoscale probe precursors formed over the dielectric layer; a plurality o... | 01/11/2011 |
| 7834424 | Extendable connector and network Extendable connectors are facilitated. According to an example embodiment, an integrated electrical circuit uses a connector that has first and second connected ends. The connector is unbundled from an initial state in which the first and second connected ends are s... | 11/16/2010 |
| 7804156 | Semiconductor wafer assembly and method of processing semiconductor wafer A semiconductor wafer assembly includes a disk-shaped semiconductor wafer including on a face side thereof a flat area having a plurality of semiconductor devices formed thereon and a beveled surface disposed around the flat surface, and a circular adhesive film bon... | 09/28/2010 |
| 7781867 | Method and system for providing an aligned semiconductor assembly A semiconductor assembly is provided that includes a first substrate that has a first surface. A second substrate is coupled to and spaced apart from the first substrate. The second substrate has a second surface facing the first surface of the first substrate. The ... | 08/24/2010 |
| 7709932 | Semiconductor wafer having a separation portion on a peripheral area A conveyance system for a semiconductor wafer can be used without any change before and after a support plate is adhered to the wafer. Also, the finish accuracy of the wafer and the positioning accuracy between the wafer and the support plate can be relaxed, thus im... | 05/04/2010 |
| 7659603 | Semiconductor and method for manufacturing the same A semiconductor device includes a substrate formed with a predetermined trench, a plurality of devices fixed into the trench, an etch stop layer on an entire surface of the substrate including the devices while selectively exposing the devices, an interlayer dielect... | 02/09/2010 |
| 7642623 | Fabrication method for polycrystalline silicon thin film and apparatus using the same The present invention relates to a fabrication method for polycrystalline silicon thin film in which amorphous silicon is crystallized by laser using a mask having a mixed structure of laser transmission pattern group and laser non-transmission pattern group, wherei... | 01/05/2010 |
| 7605447 | Highly manufacturable SRAM cells in substrates with hybrid crystal orientation The present invention relates to a semiconductor device structure that includes at least one SRAM cell formed in a substrate. Such SRAM cell comprises two pull-up transistors, two pull-down transistors, and two pass-gate transistors. The pull-down transistors and th... | 10/20/2009 |
| 7602046 | Recycling by mechanical means of a wafer comprising a multilayer structure after taking-off a thin layer thereof The invention relates to a recyclable donor wafer that includes a substrate and a formed layer thereon, wherein the formed layer has a thickness sufficient to provide (a) at least two useful layers for detachment therefrom and (b) additional material that can be rem... | 10/13/2009 |
| 7598594 | Wafer-scale microcolumn array using low temperature co-fired ceramic substrate Provided is a wafer-scale microcolumn array using a low temperature co-fired ceramic (LTCC) substrate. The microcolumn array includes a LTCC substrate having wirings and wafer-scale beam deflector arrays, which are attached to at least one side of the LTCC substrate... | 10/06/2009 |
| 7592686 | Semiconductor device having a junction extended by a selective epitaxial growth (SEG) layer and method of fabricating the same In a semiconductor device, and a method of fabricating the same, the semiconductor device includes a protrusion extending from a substrate and a selective epitaxial growth (SEG) layer surrounding an upper portion of the protrusion, the SEG layer exposing sidewalls o... | 09/22/2009 |
| 7560799 | Spacer patterned, high dielectric constant capacitor A method for fabricating a contact of a semiconductor device structure includes forming a barrier layer that is entirely recessed within a contact aperture. A central region of the barrier layer may be recessed relative to at least a portion of an outer periphery of... | 07/14/2009 |
| 7535081 | Metal nanoline process and applications on growth of aligned nanostructure thereof A metal nanoline process and applications on growth of aligned nanostructures thereof. A nano-structure is provided with a substrate with at least one nanodimensional metal catalyst line disposed thereon and at least one carbon nanotube or silicon nanowire extending... | 05/19/2009 |
| 7528463 | Semiconductor on insulator structure An apparatus and a method for forming the apparatus include a semiconductor layer on an insulating substrate, where the substrate is a different material than the semiconductor layer, and has a coefficient of thermal expansion substantially equal to that of the semi... | 05/05/2009 |
| 7521775 | Protection of three dimensional transistor structures during gate stack etch Embodiments of the invention include apparatuses and methods relating to three dimensional transistors having high-k dielectrics and metal gates with fins protected by a hard mask layer on their top surface. In one embodiment, the hard mask layer includes an oxide. | 04/21/2009 |
| 7511358 | Nonvolatile memory device having multi-bit storage and method of manufacturing the same Provided are a nonvolatile memory device having multi bit storage and a method of manufacturing the same. The method includes forming a tunneling dielectric layer, a charge storage layer and a charge blocking layer on a fin-active region, forming sacrificial pattern... | 03/31/2009 |
| 7476958 | Semiconductor wafer having different impurity concentrations in respective regions A semiconductor wafer has different impurity concentrations in respective regions and gate patterns have different lengths in the respective regions. The semiconductor wafer has different impurity concentrations in a central region, an intermediate region, and an ou... | 01/13/2009 |
