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| Number | Title | Issue Date |
| 8115282 | Memory cell device and method of manufacture According to one embodiment of the present invention, a solid state electrolyte memory cell includes a cathode, an anode and a solid state electrolyte. The anode includes an intercalating material and first metal species dispersed in the intercalating material. ... | 02/14/2012 |
| 7989924 | Switching element, programmable logic integrated circuit and memory element A switching element with a switching voltage set higher than conventional, which includes an ion conduction layer including tantalum oxide, a first electrode provided in contact with the ion conduction layer, and a second electrode provided in contact with the ion c... | 08/02/2011 |
| 7989925 | Method for forming a group III nitride material on a silicon substrate Semiconductor process technology and devices are provided, including a method for forming a high quality group III nitride layer on a silicon substrate and to a device obtainable therefrom. According to the method, a pre-dosing step is applied to a silicon substrate... | 08/02/2011 |
| 7911034 | Techniques for precision pattern transfer of carbon nanotubes from photo mask to wafers A method for patterning CNTs on a wafer wherein a CNT layer is provided on a substrate, a hard mask film is deposited on the CNT layer, a BARC layer (optional) is coated on the hard mask film, and a resist is patterned on the BARC layer (or directly on the hard mask... | 03/22/2011 |
| 7816765 | Silicon epitaxial wafer and the production method thereof A silicon epitaxial wafer obtained by growing a silicon epitaxial layer on a surface of a silicon wafer having a diameter of at least 300 mm produced by slicing a silicon single crystal ingot doped with boron and germanium grown by the Czochralski method, wherein bo... | 10/19/2010 |
| 7816764 | Method of controlling stress in gallium nitride films deposited on substrates Methods of controlling stress in GaN films deposited on silicon and silicon carbide substrates and the films produced therefrom are disclosed. A typical method comprises providing a substrate and depositing a graded gallium nitride layer on the substrate having a va... | 10/19/2010 |
| 7692272 | Electrically rewritable non-volatile memory element and method of manufacturing the same A non-volatile memory element comprises a bottom electrode 12; a top electrode 15; and a recording layer 13 containing phase change material and a block layer 14 that can block phase change of the recording layer 13, provided betwe... | 04/06/2010 |
| 7687888 | Method of controlling stress in gallium nitride films deposited on substrates Methods of controlling stress in GaN films deposited on silicon and silicon carbide substrates and the films produced therefrom are disclosed. A typical method comprises providing a substrate and depositing a graded gallium nitride layer on the substrate having a va... | 03/30/2010 |
| 7683457 | Group I-VII semiconductor single crystal thin film and process for producing same A CaF2 buffer layer (3) is formed on a CaF2 (111) substrate (2) by an MBE method. Furthermore, a CuCl thin film is grown on the CaF2 buffer layer (3) by the MBE method while irradiating it with an electron beam t... | 03/23/2010 |
| 7642622 | Phase changeable memory cells and methods of forming the same A phase changeable memory cell is provided. The phase changeable memory cell includes a lower interlayer dielectric layer formed on a semiconductor substrate and a lower conductive plug passing through the lower interlayer dielectric layer. The lower conductive plug... | 01/05/2010 |
| 7573122 | Method for producing a semiconductor component having a metallic control electrode, and semiconductor component A method for producing a semiconductor component, and a semiconductor component, having a metallic gate electrode deposited onto a semiconductor layer, with the gate electrode having a gate foot and a gate head. The component is produced by depositing a first layer ... | 08/11/2009 |
| 7569913 | Boron etch-stop layer and methods related thereto A method for forming an etch-stop layer and a resulting structure fabricated therefrom. The etch-stop layer has a semiconductor layer having a first surface and a boron layer formed below the first surface of the semiconductor layer. The boron layer has a full-width... | 08/04/2009 |
| 7528462 | Aluminum nitride single-crystal multi-layered substrate An aluminum nitride single-crystal multi-layered substrate comprising an aluminum nitride single-crystal layer formed by direct reduction nitridation on a single-crystal α-alumina substrate such as a sapphire substrate and an edge-type dislocation layer having a th... | 05/05/2009 |
| 7482674 | Crystalline III-V nitride films on refractory metal substrates An article of manufacture having a substrate having a top surface and a first layer on the top surface. The top surface contains titanium carbide, vanadium carbide, zirconium carbide, niobium carbide, hafnium carbide, tantalum carbide, tungsten carbide, chromium nit... | 01/27/2009 |
| 7470971 | Anodically bonded ultra-high-vacuum cell The present invention discloses an anodically bonded vacuum cell structure with a glass substrate including a cavity, and a substrate deposited on the glass substrate, thereby enclosing the cavity to form a bonding interface. The bonding interface having silicon suc... | 12/30/2008 |
| 7456488 | Porogen material A porogen material for forming a dielectric porous film. The porogen material may include a silicon based dielectric precursor and a silicon containing porogen. The porous film may have a substantially uniform dielectric constant value throughout. Methods of forming... | 11/25/2008 |
| 7436045 | Gallium nitride-based semiconductor device A gallium nitride-based semiconductor device has a p-type layer that is a gallium nitride (GaN) compound semiconductor layer containing a p-type impurity and exhibiting p-type conduction. The p-type layer includes a top portion and an inner portion located under the... | 10/14/2008 |
| 7408240 | Memory device A phase change memory cell is disclosed. The phase change memory cell includes a first thin film spacer and a second thin film spacer. The first thin film spacer defines a sub-lithographic dimension and is electrically coupled to a first electrode. The second thin f... | 08/05/2008 |
| 7368793 | HEMT transistor semiconductor device The semiconductor device of the present invention includes a device formation region formed on a substrate and including at least one semiconductor region, and a first electrode and a second electrode formed spaced apart from each other on the device formation regio... | 05/06/2008 |
| 7357837 | GaN single crystal substrate and method of making the same The method of making a GaN single crystal substrate comprises a mask layer forming step of forming on a GaAs substrate 2 a mask layer 8 having a plurality of opening windows 10 disposed separate from each other; and an epitaxial layer growing st... | 04/15/2008 |
| 7349246 | Initial firing method and phase change memory device for performing firing effectively In a firing method of a phase change memory device and a phase change memory capable of effectively performing a firing operation, the phase change memory device includes a plurality of memory cell array blocks, a counter clock generation unit, a decoding unit, and ... | 03/25/2008 |
| 7339187 | Transistor structures Enhancement mode, field effect transistors wherein at least a portion of the transistor structure may be substantially transparent. One variant of the transistor includes a channel layer comprising a substantially insulating, substantially transparent, material sele... | 03/04/2008 |
| 7323675 | Packaging structure of a light-sensing device with a spacer wall The present invention discloses a packaging structure of a light-sensing device with a spacer wall, wherein a spacer wall is used to protect the light-sensing region from external pollutants or two spacer walls are used to confine the glue to therebetween lest the o... | 01/29/2008 |
| 7323764 | Buffer structure for modifying a silicon substrate A buffer structure comprising a compositionally graded layer of a nitride alloy comprising two or more Group IIIB elements, for example La, Y, Sc or Ac, is used to modify a silicon substrate to produce a universal substrate on which a range of target materials, for ... | 01/29/2008 |
| 7319057 | Phase change material memory device A lower electrode may be covered by a protective film to reduce the exposure of the lower electrode to subsequent processing steps or the open environment. As a result, materials that may have advantageous properties as lower electrodes may be utilized despite the f... | 01/15/2008 |
| 7317242 | Semiconductor device including p-type silicon layer including implanted germanium The invention provides a semiconductor device having a pn diode that includes a p-type SiGe layer and a n-type Si layer junctioned to the p-type SiGe layer. A built-in potential of the pn diode can be reduced, and thus obtaining a diode characteristics with lower im... | 01/08/2008 |
| 7307290 | Compound semiconductor wafer and manufacturing method thereof A compound semiconductor wafer providing an InGaAs light receiving layer having superior crystal characteristic suitable for a near-infrared sensor includes an InAsxP1-x graded buffer layer consisting of a plurality of layers positioned on an I... | 12/11/2007 |
| 7304368 | Chalcogenide-based electrokinetic memory element and method of forming the same Memory elements including a first electrode and a second electrode. A chalcogenide material layer is between the first and second electrodes and a tin-chalcogenide layer is between the chalcogenide material layer and the second electrode. A selenide layer is between... | 12/04/2007 |
| 7297977 | Semiconductor device One exemplary embodiment includes a semiconductor device. The semiconductor device comprising a channel including one or more of a metal oxide including zinc-gallium, cadmium-gallium, cadmium-indium. ... | 11/20/2007 |
| 7282783 | Resistance variable memory device and method of fabrication Methods and apparatus for providing a resistance variable memory device with agglomeration prevention and thermal stability. According to one embodiment, a resistance variable memory device is provided having at least one tin-chalcogenide layer proximate at least on... | 10/16/2007 |
| 7282782 | Combined binary oxide semiconductor device A semiconductor device can include a channel including a first binary oxide and a second binary oxide. ... | 10/16/2007 |
| 7279047 | Reactor for extended duration growth of gallium containing single crystals An apparatus for growing bulk GaN and AlGaN single crystal boules, preferably using a modified HVPE process, is provided. The single crystal boules typically have a volume in excess of 4 cubic centimeters with a minimum dimension of approximately 1 centimeter. If de... | 10/09/2007 |
| 7276779 | III-V group nitride system semiconductor substrate A III-V group nitride system semiconductor substrate is of a III-V group nitride system single crystal. The III-V group nitride system semiconductor substrate has a flat surface, and a vector made by projecting on a surface of the substrate a normal vector of a low ... | 10/02/2007 |
| 7260939 | Thermal transfer device and system and method incorporating same A method of manufacturing a thermal transfer device including providing first and second thermally conductive substrates that are substantially atomically flat, providing a patterned electrical barrier having a plurality of closed shapes on the first thermally condu... | 08/28/2007 |
| 7253499 | III-V group nitride system semiconductor self-standing substrate, method of making the same and III-V group nitride system semiconductor wafer A III-V group nitride system semiconductor self-standing substrate has III-V group nitride system semiconductor single crystal with a hexagonal crystal system crystalline structure. The substrate is provided with a polished surface at every position of which crystal... | 08/07/2007 |
| 7254055 | Initial firing method and phase change memory device for performing firing effectively In a firing method of a phase change memory device and a phase change memory capable of effectively performing a firing operation, the phase change memory device includes a plurality of memory cell array blocks, a counter clock generation unit, a decoding unit, and ... | 08/07/2007 |
| 7245017 | Liquid discharge head and manufacturing method thereof The liquid discharge head has a three-dimensional structure which defines a space including a pressure chamber filled with liquid and a flow channel for supplying the liquid to the pressure chamber, the three-dimensional structure being formed by depositing a compos... | 07/17/2007 |
| 7238425 | Telescoped multiwall nanotube and manufacture thereof The invention relates to a method for forming a telescoped multiwall nanotube. Such a telescoped multiwall nanotube may find use as a linear or rotational bearing in microelectromechanical systems or may find use as a constant force nanospring. In the method of the ... | 07/03/2007 |
| 7235920 | Display device and method of its manufacture A display device and method for its manufacture. In a display device with a first array of individual display elements and a second array of control transistors for the display elements, control transistors are formed from a semiconductor material with a large band ... | 06/26/2007 |
| 7233054 | Phase change material and non-volatile memory device using the same The present invention provides a phase change memory cell comprising (GeASbBTeC)1-X(RaSbTeC)X solid solution, the solid solution being formed from a Ge—Sb—Te based alloy and ... | 06/19/2007 |
