Bizarre Patents
User-operated amusement apparatus for kicking the user's buttocks
An apparatus including a user-operated and controlled apparatus for self-infliction of repetitive blows to the user's buttocks by a plurality of elongated arms bearing flexible extensions that rotate under the user's control.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8138576 | Production method and production apparatus of tin or solder alloy for electronic components, and solder alloy The invention provides a technique and a device that dramatically improve joint reliability of miniature joints of fine electronic components. According to the invention, when producing a tin or a solder alloy used for electronic components, an ingot of a tin or a s... | 03/20/2012 |
| 7791172 | Nonvolatile semiconductor memory device The invention relates to a nonvolatile semiconductor memory device including a semiconductor layer which has a source region, a drain region, and a channel forming region which is provided between the source region and the drain region; and a first insulating layer,... | 09/07/2010 |
| 7432538 | Field-effect transistor A field-effect transistor includes a channel layer having a channel and a carrier supply layer, disposed on the channel layer, containing a semiconductor represented by the formula AlxGa1-xN, wherein x is greater than 0.04 and less than 0.45. T... | 10/07/2008 |
| 7282781 | Semiconductor device with a short-lifetime region and manufacturing method thereof A semiconductor device has an n−-semiconductor layer and p+-diffusion regions each having a depth of 14 to 20 μm (design value) selectively formed in the n− semiconductor layer. With the entire surface of the chip irradiated wit... | 10/16/2007 |
| 7259428 | Semiconductor device using SOI structure having a triple-well region A semiconductor device includes a support substrate, a buried insulation film, provided on the support substrate, having a thickness of 5 to 10 nm, a silicon layer provided on the buried insulation film, a MOSFET provided in the silicon layer, and a triple-well regi... | 08/21/2007 |
| 7242037 | Process for making non-uniform minority carrier lifetime distribution in high performance silicon power devices An electronic power device comprising a single crystal silicon segment being characterized in that the segment comprises a non-uniform distribution of minority carrier recombination centers, the minority carrier recombination centers comprising a substitutional meta... | 07/10/2007 |
| 7187057 | Nitrogen controlled growth of dislocation loop in stress enhanced transistor Known techniques to improve metal-oxide-semiconductor field effect transistor (MOSFET) performance is to add a high stress dielectric layer to the MOSFET. The high stress dielectric layer introduces stress in the MOSFET that causes electron mobility drive current to... | 03/06/2007 |
| 7087981 | Metal semiconductor contact, semiconductor component, integrated circuit arrangement and method The present invention relates to a metal-semiconductor contact comprising a semiconductor layer and comprising a metallization applied to the semiconductor layer, a high dopant concentration being introduced into the semiconductor layer such that a non-reactive meta... | 08/08/2006 |
| 7030464 | Semiconductor device and method of manufacturing the same A technology of restraining junction leakage in a semiconductor device is to be provided. There is provided a semiconductor device provided with a semiconductor substrate, a gate electrode 9 formed on the semiconductor substrate, and a source/drain region for... | 04/18/2006 |
| 6888171 | Light emitting diode A semi-conductor light emitting diode includes closely spaced n and p electrodes formed on the same side of a substrate to form an LED with a small foot-print. A semi-transparent U shaped p contact layer is formed along three sides of the top surface of the underlyi... | 05/03/2005 |
| 6870199 | Semiconductor device having an electrode overlaps a short carrier lifetime region A semiconductor device that helps to prevent the occurrence of current localization in the vicinity of an electrode edge and improves the reverse-recovery withstanding capability. The semiconductor device according to the invention includes a first carrier lifetime ... | 03/22/2005 |
| 6853084 | Substrate within a Ni/Au structure electroplated on electrical contact pads and method for fabricating the same The present invention discloses a substrate within a Ni/Au structure electroplated on electrical contact pads and a method for fabricating the same. The method comprises: providing a substrate with a circuit layout pattern and forming a conducting film on the surfac... | 02/08/2005 |
| 6828690 | Non-uniform minority carrier lifetime distributions in high performance silicon power devices A process for heat-treating a single crystal silicon segment to influence the profile of minority carrier recombination centers in the segment. The segment has a front surface, a back surface, and a central plane between the front and back surfaces. In the process, ... | 12/07/2004 |
| 6744116 | Thin film using non-thermal techniques A method for forming an integrated circuit is provided. A semiconductor film is formed onto a first substrate. A metal film is formed onto a second substrate. The second substrate is bonded with the metal film onto the thin film of the first substrate. A first layer... | 06/01/2004 |
| 6727147 | MOSFET fabrication method An FET is fabricated on an SOI substrate by the following processes. Openings are formed in laminated layers of a pad oxide film of about 5-10 nm and an oxidation-resistant nitride film of about 50-150 nm at positions where device isolation regions are to be provide... | 04/27/2004 |
| 6713819 | SOI MOSFET having amorphized source drain and method of fabrication An integrated circuit formed in semiconductor-on-insulator format. The integrated circuit includes a layer of semiconductor material disposed on an insulating layer, where the insulating layer disposed on a substrate. A first and a second MOSFET are provided such th... | 03/30/2004 |
| 6639327 | Semiconductor member, semiconductor device and manufacturing methods thereof In a bonded semiconductor member, microgaps are formed on a substrate side of a bonding interface to thereby constitute a gettering site, and heavy metal elements contaminated in the substrate are captured by the microgaps. The bonded semiconductor member... | 10/28/2003 |
| 6621101 | Thin-film transistor The present invention provides, in a TFT, a channel region facing a gate electrode through a gate insulating film, a source electrode connected to the channel region and a drain region connected to the channel region on the side opposite the source region... | 09/16/2003 |
| 6605830 | Power semiconductor device including an IGBT with a MOS transistor as a current suppressing device incorporated therein A power semiconductor device including first and second assembly units. The first assembly of units includes a first semiconductor region of a second conductivity type selectively formed in a first main surface of the first semiconductor layer, a second s... | 08/12/2003 |
| 6603189 | Semiconductor device with deliberately damaged layer having a shorter carrier lifetime therein A technique of improving a reverse recovery characteristic of a semiconductor device which solves a technical problem of breakdown voltage reduction which has conventionally caused in enhancing soft recover. To solve the technical problem, in a PN junctio... | 08/05/2003 |
| 6552414 | Semiconductor device with selectively diffused regions The present invention describes a method of manufacturing a semiconductor device, comprising a semiconductor substrate (2) in the shape of a slice, the method comprising the steps of: step 1) selectively applying a pattern of a solids-based dopant source ... | 04/22/2003 |
| 6498387 | Wafer level package and the process of the same The present invention includes polishing the wafer backside by a grinder. Subsequently, a glass is laminated on the wafer backside surface by using epoxy. Then, the wafer is etched to isolate the dies. An epoxy is then coated on the wafer by means of vacu... | 12/24/2002 |
| 6423570 | Method to protect an encapsulated die package during back grinding with a solder metallization layer and devices formed thereby A microelectronic package including a microelectronic die having an active surface and at least one side. An encapsulation material is disposed adjacent the microelectronic die side(s). A portion of the encapsulation material is removed to expose a back s... | 07/23/2002 |
| 6294828 | Semiconductor chip package A method for joining a semiconductor integrated circuit chip in a flip chip configuration, via solder balls, to solderable metal contact pads, leads or circuit lines on the circuitized surface of an organic chip carrier substrate, as well as the resulting... | 09/25/2001 |
| 6281521 | Silicon carbide horizontal channel buffered gate semiconductor devices Silicon carbide channel semiconductor devices are provided which eliminate the insulator of the gate by utilizing a semiconductor gate layer and buried base regions to create a "pinched off" gate region when no bias is applied to the gate. In particular e... | 08/28/2001 |
| 6177685 | Nitride-type III-V HEMT having an InN 2DEG channel layer A nitride-type III-V group compound semiconductor device includes a substrate and a layered structure including at least a channel layer using two-dimensional electron gas formed over a substrate, wherein the channel layer contains InN.... | 01/23/2001 |
| 6153920 | Process for controlling dopant diffusion in a semiconductor layer and semiconductor device formed thereby A semiconductor device having a carbon-containing region with an advantageous concentration profile is disclosed. The carbon is introduced into a region of the substrate and at a depth below the space-charge layer of the device and at a concentration such... | 11/28/2000 |
| 6075259 | Power semiconductor devices that utilize buried insulating regions to achieve higher than parallel-plane breakdown voltages Power semiconductor devices include a semiconductor substrate having a face thereon and a buried electrically insulating layer extending laterally in the semiconductor substrate and having an opening therein. A drift region of first conductivity type is a... | 06/13/2000 |
| 6071751 | Deuterium sintering with rapid quenching Channel-hot-carrier reliability can be improved by deuterium sintering. However, the benefits obtained by deuterium sintering can be greatly reduced or destroyed by thermal processing steps which break Si--H and Si--D bonds. A solution is to increase the ... | 06/06/2000 |
| 5909051 | Minority carrier semiconductor devices with improved stability A method for improving the operating stability of compound semiconductor minority carrier devices and the devices created using this method are described. The method describes intentional introduction of impurities into the layers adjacent to the active r... | 06/01/1999 |
| 5856698 | Second implanted matrix for agglomeration control and thermal stability A semiconductor device on a semiconductor wafer, wherein improvements are realized to agglomeration control, resistivity, and thermal stability of a titanium disilicide layer on a polysilicon layer. Agglomeration control is achieved through the use of two... | 01/05/1999 |
| 5739559 | Compound semiconductor integrated circuit with a particular high resistance layer A compound semiconductor integrated circuit having a high resistance layer consisting of a compound semiconductor to which oxygen is added as an impurity and an undoped compound semiconductor layer which are formed between a semi-insulating substrate and ... | 04/14/1998 |
| 5717244 | Semiconductor device having layers with varying lifetime characteristics An N- layer (11) of a low impurity concentration is formed on an upper major surface of an N+ layer (13) of a high impurity concentration in a diode (10). A P layer (12) is further formed on its upper major surface. The N-... | 02/10/1998 |
| 5578865 | Reduction of parasitic effects in floating body mosfets A semiconductor fabrication method improves the voltage characteristic of floating-body MOSFETs by creating recombination centers near the source-body junction of the device. A MOSFET is fabricated through the passivation oxidation stage, and a photolitho... | 11/26/1996 |
| 5569953 | Semiconductor device having an isolation region enriched in oxygen A method for growing an epitaxial layer of a group III-V compound semiconductor material that contains oxygen comprises the steps of supplying molecules of an organic compound that contains a group V element and oxygen in the molecule, and decomposing the... | 10/29/1996 |
| 5543637 | Silicon carbide semiconductor devices having buried silicon carbide conduction barrier layers therein A silicon carbide semiconductor device includes a silicon carbide substrate, an active layer in the substrate and a silicon carbide buried layer which provides a conduction barrier between the substrate and at least a portion of the active layer. The buri... | 08/06/1996 |
| 5436498 | Gettering of impurities by forming a stable chemical compound Reactor atoms (22) are introduced into a silicon substrate (10) by ion implantation to combine with metal impurities (18) to form stable chemical compounds (24). The stable compounds do not decompose and release the metal impurities during subsequent proc... | 07/25/1995 |
| 5426329 | Semiconductor device with arsenic doped silicon thin film interconnections or electrodes A principal feature of the present invention is to obtain a semiconductor device including a silicon thin film for use as interconnections or an electrode. The semiconductor device includes a semiconductor substrate, and a silicon thin film provided on th... | 06/20/1995 |
| 5384477 | CMOS latchup suppression by localized minority carrier lifetime reduction A unique approach to suppressing latchup in CMOS structures is described. Atomic species that exhibit midgap levels in silicon and satisfy the criteria for localized action and electrical compatibility can be implanted to suppress the parasitic bipolar be... | 01/24/1995 |
| 5357130 | Low-noise cryogenic MOSFET A microelectronic device of the MOSFET type (20) is structured to exhibit low noise characteristics at cryogenic temperatures of less than about 40K. The device (20) comprises a doped silicon substrate wafer (22), the dopant having an ionization energy in... | 10/18/1994 |
