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| Number | Title | Issue Date |
| 8183666 | Semiconductor device including semiconductor zones and manufacturing method A semiconductor device includes first semiconductor zones of a first conductivity type having a first dopant species of the first conductivity type and a second dopant species of a second conductivity type different from the first conductivity type. The semiconducto... | 05/22/2012 |
| 8035196 | Methods of counter-doping collector regions in bipolar transistors The present invention provides a method of forming a bipolar transistor. The method includes doping a silicon layer with a first type of dopant and performing a first implant process to implant dopant of a second type opposite the first type in the silicon layer. Th... | 10/11/2011 |
| 7994612 | FinFETs single-sided implant formation A method patterns pairs of semiconducting fins on an insulator layer and then patterns a linear gate conductor structure over and perpendicular to the fins. Next, the method patterns a mask on the insulator layer adjacent the fins such that sidewalls of the mask are... | 08/09/2011 |
| 7880272 | Semiconductor device with near-surface compensation doping area and method of fabricating Aspects of the present invention include a semiconductor device and method. In a transition region of a semiconductor material region, a near-surface compensation doping area with a conductivity type, which is different than the conductivity type of a transition dop... | 02/01/2011 |
| 7786550 | P-type semiconductor and semiconductor hetero material and manufacturing methods thereof A p-type semiconductor includes a host material that is a semiconductor, an acceptor element and a localized band formation element. The acceptor element is doped to the host material and has fewer valence electrons than valance electrons of at least one of the elem... | 08/31/2010 |
| 7492035 | Semiconductor device and method of manufacturing the same A semiconductor device has a semiconductor substrate and a high-resistance first conductivity type well region disposed on the semiconductor substrate. A low-resistance second conductivity type source region and a low-resistance second conductivity type drain region... | 02/17/2009 |
| 7432538 | Field-effect transistor A field-effect transistor includes a channel layer having a channel and a carrier supply layer, disposed on the channel layer, containing a semiconductor represented by the formula AlxGa1-xN, wherein x is greater than 0.04 and less than 0.45. T... | 10/07/2008 |
| 7422801 | Electroluminescent fluorescent substance An electroluminescent fluorescent substance, which is composed of electroluminescent fluorescent particles having an average particle diameter of 0.5 μm to 20 μm and a variation coefficient of particle diameter of 35% or less, and having at least 50% have stacking... | 09/09/2008 |
| 7417248 | Transistor with shallow germanium implantation region in channel A method of manufacturing a transistor and a structure thereof, wherein a very shallow region having a high dopant concentration of germanium is implanted into a channel region of a transistor at a low energy level, forming an amorphous germanium implantation region... | 08/26/2008 |
| 7404157 | Evaluation device and circuit design method used for the same There is provided an evaluation apparatus capable of measuring the I-V characteristic in the MOSFET AC operation with a high accuracy. There are also provided a circuit design method and a circuit design system used for the evaluation apparatus. In the evaluation ap... | 07/22/2008 |
| 7397110 | High resistance silicon wafer and its manufacturing method A high-resistance silicon wafer is manufactured in which a gettering ability, mechanical strength, and economical efficiency are excellent and an oxygen thermal donor is effectively prevented from being generated in a heat treatment for forming a circuit, which is i... | 07/08/2008 |
| 7288819 | Stable PD-SOI devices and methods One aspect of the present subject matter relates to a partially depleted silicon-on-insulator structure. The structure includes a well region formed above an oxide insulation layer. In various embodiments, the well region is a multilayer epitaxy that includes a sili... | 10/30/2007 |
| 7268022 | Stable PD-SOI devices and methods One aspect of the present subject matter relates to a partially depleted silicon-on-insulator structure. The structure includes a well region formed above an oxide insulation layer. In various embodiments, the well region is a multilayer epitaxy that includes a sili... | 09/11/2007 |
| 7265435 | Method for implanting atomic species through an uneven surface of a semiconductor layer A method for implanting atomic species through an uneven surface of a semiconductor layer. The technique includes applying a covering layer upon the uneven surface in an amount sufficient and in a manner to increase surface uniformity. The method also includes impla... | 09/04/2007 |
| 7259428 | Semiconductor device using SOI structure having a triple-well region A semiconductor device includes a support substrate, a buried insulation film, provided on the support substrate, having a thickness of 5 to 10 nm, a silicon layer provided on the buried insulation film, a MOSFET provided in the silicon layer, and a triple-well regi... | 08/21/2007 |
| 7242075 | Silicon wafers and method of fabricating the same By using a two-step RTP (rapid thermal processing) process, the wafer is provided which has an ideal semiconductor device region secured by controlling fine oxygen precipitates and OiSFs (Oxidation Induced Stacking Fault) located on the surface region of the wafer. ... | 07/10/2007 |
| 7242037 | Process for making non-uniform minority carrier lifetime distribution in high performance silicon power devices An electronic power device comprising a single crystal silicon segment being characterized in that the segment comprises a non-uniform distribution of minority carrier recombination centers, the minority carrier recombination centers comprising a substitutional meta... | 07/10/2007 |
| 7235863 | Silicon wafer and process for producing it A process for producing a single-crystal silicon wafer, comprises the following steps: producing a layer on the front surface of the silicon wafer by epitaxial deposition or production of a layer whose electrical resistance differs... | 06/26/2007 |
| 7221037 | Method of manufacturing group III nitride substrate and semiconductor device The present invention provides a method of manufacturing a Group III nitride substrate that has less variations in in-plane carrier concentration and includes crystals grown at a high growth rate. The manufacturing method of the present invention includes: (i) formi... | 05/22/2007 |
| 7217975 | Lateral type semiconductor device A lateral semiconductor device includes: a semiconductor substrate formed on a base region therein; a plurality of emitter regions with a triangle arrangement in an upper part of the base layer and collector regions surrounding the emitter regions, respectively, apa... | 05/15/2007 |
| 7187057 | Nitrogen controlled growth of dislocation loop in stress enhanced transistor Known techniques to improve metal-oxide-semiconductor field effect transistor (MOSFET) performance is to add a high stress dielectric layer to the MOSFET. The high stress dielectric layer introduces stress in the MOSFET that causes electron mobility drive current to... | 03/06/2007 |
| 7141490 | Method of fabricating a semiconductor device In a manufacturing process of a semiconductor device using a substrate having low heat resistance, such as a glass substrate, there is provided a method of efficiently carrying out crystallization of a semiconductor film and gettering treatment of a catalytic elemen... | 11/28/2006 |
| 7129521 | Semiconductor device and manufacture method thereof The problem is to provide a technology to reduce a light leakage current in order to obtain a good display. One kind or plurality kinds of elements chosen from argon, germanium, silicon, helium, neon, krypton, and xenon are implanted in a crystalline semiconductor l... | 10/31/2006 |
| 7081664 | Doped semiconductor powder and preparation thereof The invention provides a doped semiconductor powder comprising nanocrystals of a group IV semiconductor and a rare earth element, the rare earth element being dispersed on the surface of the group IV semiconductor nanocrystals. The invention also provides processes ... | 07/25/2006 |
| 7078357 | Method for manufacturing silicon wafer and silicon wafer There are provided a heat-treating method capable of both increasing BMD density and widening DZ layer width, and a silicon wafer having DZ layer width wider compared with a conventional one regardless of high BMD density. In the method, heat treatment (RTA treatmen... | 07/18/2006 |
| 7071515 | Narrow width effect improvement with photoresist plug process and STI corner ion implantation A method to reduce the inverse narrow width effect in NMOS transistors is described. An oxide liner is deposited in a shallow trench that is formed to isolate active areas in a substrate. A photoresist plug is formed in the shallow trench and is recessed below the t... | 07/04/2006 |
| 7061049 | Semiconductor device using SOI device and semiconductor integrated circuit using the semiconductor device A semiconductor device includes a semiconductor layer provided on a semiconductor substrate with an insulating film interposed therebetween. A gate electrode is provided on the semiconductor layer with a gate insulating film interposed therebetween, and a pair of so... | 06/13/2006 |
| 7037814 | Single mask control of doping levels In an integrated circuit, dopant concentration levels are adjusted by making use of a perforated mask. Doping levels for different regions across an integrated circuit can be differently defined by making use of varying size and spacings to the perforations in the m... | 05/02/2006 |
| 7030464 | Semiconductor device and method of manufacturing the same A technology of restraining junction leakage in a semiconductor device is to be provided. There is provided a semiconductor device provided with a semiconductor substrate, a gate electrode 9 formed on the semiconductor substrate, and a source/drain region for... | 04/18/2006 |
| 6989567 | LDMOS transistor A semiconductor transistor structure includes a substrate having an epitaxial layer, a source region extending from the surface of the epitaxial layer, a drain region within the epitaxial layer, a channel located between the drain and source regions, and a gate arra... | 01/24/2006 |
| 6933589 | Method of making a semiconductor transistor Transistors are manufactured by growing germanium source and drain regions, implanting dopant impurities into the germanium, and subsequently annealing the source and drain regions so that the dopant impurities diffuse through the germanium. The process is simpler t... | 08/23/2005 |
| 6878579 | Semiconductor device and method of manufacturing the same An aspect of the present invention includes a first conductive type semiconductor region; a gate electrode formed on the first conductive type semiconductor region; a channel region formed immediately below the gate electrode in the first conductive type semiconduct... | 04/12/2005 |
| 6855959 | Nitride based semiconductor photo-luminescent device A nitride based semiconductor photo-luminescent device has an active layer having a quantum well structure. The active layer has both a high dislocation density region and a low dislocation density region that is lower in dislocation density than the high dislocatio... | 02/15/2005 |
| 6828655 | Semiconductor film with low crystal defect and semiconductor device and display apparatus using the semiconductor film A semiconductor film comprising a polycrystalline semiconductor film provided on a substrate having an insulating surface. Nearly all crystal orientation angle differences between adjacent crystal grains constituting the polycrystalline semiconductor film are presen... | 12/07/2004 |
| 6828690 | Non-uniform minority carrier lifetime distributions in high performance silicon power devices A process for heat-treating a single crystal silicon segment to influence the profile of minority carrier recombination centers in the segment. The segment has a front surface, a back surface, and a central plane between the front and back surfaces. In the process, ... | 12/07/2004 |
| 6806147 | Method and apparatus for suppressing the channeling effect in high energy deep well implantation The invention provides an improved well structure for electrically separating n-channel and p-channel MOSFETs. The invention first forms a shallow well in a substrate. A buried amorphous layer is then formed below the shallow well. A deep well is then formed below t... | 10/19/2004 |
| 6791106 | Semiconductor device and method of manufacturing the same An aspect of the present invention includes a first conductive type semiconductor region; a gate electrode formed on the first conductive type semiconductor region; a channel region formed immediately below the gate electrode in the first conductive type semiconduct... | 09/14/2004 |
| 6777732 | Random access memory A process for enhancing refresh in Dynamic Random Access Memories wherein n-type impurities are implanted into the capacitor buried contact after formation of the access transistor components. The process comprises forming a gate insulating layer on a substrate and ... | 08/17/2004 |
| 6744116 | Thin film using non-thermal techniques A method for forming an integrated circuit is provided. A semiconductor film is formed onto a first substrate. A metal film is formed onto a second substrate. The second substrate is bonded with the metal film onto the thin film of the first substrate. A first layer... | 06/01/2004 |
| 6639327 | Semiconductor member, semiconductor device and manufacturing methods thereof In a bonded semiconductor member, microgaps are formed on a substrate side of a bonding interface to thereby constitute a gettering site, and heavy metal elements contaminated in the substrate are captured by the microgaps. The bonded semiconductor member... | 10/28/2003 |
