Bizarre Patents
A portable partition for use in an automobile having a seat with a seat bench and a seat backrest.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8188568 | Semiconductor integrated circuit A semiconductor circuit includes: a first diffusion layer formed on a substrate; a second diffusion layer formed in an upper part of the first diffusion layer; a third diffusion layer formed in an upper part of the second diffusion layer; a fourth diffusion layer fo... | 05/29/2012 |
| 7911024 | Ultra-thin SOI vertical bipolar transistors with an inversion collector on thin-buried oxide (BOX) for low substrate-bias operation and methods thereof The present invention provides a “collector-less” silicon-on-insulator (SOI) bipolar junction transistor (BJT) that has no impurity-doped collector. Instead, the inventive vertical SOI BJT uses a back gate-induced, minority carrier inversion layer as the intrins... | 03/22/2011 |
| 7576406 | Semiconductor device A plurality of the same kind of npn-type bipolar transistors are disposed regularly on a semiconductor layer that is provided over an insulation layer. The plurality of unit bipolar transistors are connected in parallel, thereby to form a plurality of desired bipola... | 08/18/2009 |
| 7492031 | Semiconductor device A semiconductor device comprises a first base layer of a first conductive type which has a first surface and a second surface; a second base layer of a second conductive type which is formed on the first surface; first and second gate electrodes which are formed by ... | 02/17/2009 |
| 7466008 | BiCMOS performance enhancement by mechanical uniaxial strain and methods of manufacture A BiCMOS device with enhanced performance by mechanical uniaxial strain is provided. A first embodiment of the present invention includes an NMOS transistor, a PMOS transistor, and a bipolar transistor formed on different areas of the substrate. A first contact etch... | 12/16/2008 |
| 7439607 | Beta control using a rapid thermal oxidation A method of forming semiconductor device treating a surface of a substrate to produce a discontinuous growth of a material on the surface through rapid thermal oxidation of the substrate surface at a temperature of less than about 700° C. ... | 10/21/2008 |
| 7420228 | Bipolar transistor comprising carbon-doped semiconductor A bipolar transistor comprising a collector region of a first conduction type, and a subcollector region of the first conduction type at a first side of the collector region. The transistor further includes a base region of the second conduction type provided at a s... | 09/02/2008 |
| 7397070 | Self-aligned transistor In one embodiment, a transistor is formed to use two conductors to make electrical connection to one of the active regions of the transistor. ... | 07/08/2008 |
| 7375410 | Ultra-thin SOI vertical bipolar transistors with an inversion collector on thin-buried oxide (BOX) for low substrate-bias operation and methods thereof The present invention provides a “collector-less” silicon-on-insulator (SOI) bipolar junction transistor (BJT) that has no impurity-doped collector. Instead, the inventive vertical SOI BJT uses a back gate-induced, minority carrier inversion layer as the intrins... | 05/20/2008 |
| 7355263 | Semiconductor device and manufacturing method thereof A semiconductor device and method of manufacturing the same includes an n−-single crystal silicon substrate, with an oxide film selectively formed thereon. On the oxide film, gate polysilicon is formed. The surface of the gate polysilicon is covered wit... | 04/08/2008 |
| 7342293 | Bipolar junction transistors (BJTS) with second shallow trench isolation (STI) regions, and methods for forming same The present invention relates to bipolar junction transistors (BJTS). The collector region of each BJT is located in a semiconductor substrate surface and adjacent to a first shallow trench isolation (STI) region. A second STI region is provided, which extends betwe... | 03/11/2008 |
| 7339254 | SOI substrate for integration of opto-electronics with SiGe BiCMOS According to an exemplary embodiment, a structure includes a silicon-on-insulator substrate including a buried oxide layer situated over a bulk silicon substrate and a silicon layer situated over the buried oxide layer. The structure further includes a trench formed... | 03/04/2008 |
| 7332752 | Optoelectronic circuit employing a heterojunction thyristor device to convert a digital optical signal to a digital electrical signal An optoelectronic circuit includes a resonant cavity formed on a substrate and into which is injected an input digital optical signal that encodes bits of information (each bit representing an OFF logic level or an ON logic level). A heterojunction thyristor device,... | 02/19/2008 |
| 7300850 | Method of forming a self-aligned transistor In one embodiment, a transistor is formed to use two conductors to make electrical connection to one of the active regions of the transistor. ... | 11/27/2007 |
| 7271070 | Method for producing transistors The invention relates to a method for producing integrable semiconductor components, especially transistors or logic gates, using a p-doped semiconductor substrate. First of all, a mask is applied to the semiconductor substrate in order to define a window that is de... | 09/18/2007 |
| 7262478 | Semiconductor device and manufacturing method thereof A semiconductor device and method of manufacturing the same includes an n−-single crystal silicon substrate, with an oxide film selectively formed thereon. On the oxide film, gate polysilicon is formed. The surface of the gate polysilicon is covered wit... | 08/28/2007 |
| 7242071 | Semiconductor structure A structure comprises a deep sub-collector buried in a first epitaxial layer and a near sub-collector buried in a second epitaxial layer. The structure further comprises a deep trench isolation structure isolating a region which is substantially above the deep sub-c... | 07/10/2007 |
| 7173320 | High performance lateral bipolar transistor A lateral bipolar transistor includes an emitter region, a base region, a collector region, and a gate disposed over the base region. A bias line is connected to the gate for applying a bias voltage thereto during operation of the transistor. The polarity of the bia... | 02/06/2007 |
| 7157785 | Semiconductor device, the method of manufacturing the same, and two-way switching device using the semiconductor devices A semiconductor device is disclosed that reduces the reverse leakage current caused by reverse bias voltage application and reduces the on-voltage of the IGBT. A two-way switching device using the semiconductor devices is provided, and a method of manufacturing the ... | 01/02/2007 |
| 7115965 | Vertical bipolar transistor with a majority carrier accumulation layer as a subcollector for SOI BiCMOS with reduced buried oxide thickness for low-substrate bias operation The present invention provides a “subcollector-less” silicon-on-insulator (SOI) bipolar junction transistor (BJT) that has no impurity-doped subcollector. Instead, the inventive vertical SOI BJT uses a back gate-induced, majority carrier accumulation layer as th... | 10/03/2006 |
| 7095094 | Multiple doping level bipolar junctions transistors and method for forming A process for forming bipolar junction transistors having a plurality of different collector doping densities on a semiconductor substrate and an integrated circuit comprising bipolar junction transistors having a plurality of different collector doping densities. A... | 08/22/2006 |
| 7071516 | Semiconductor device and driving circuit for semiconductor device A PMOS transistor (Q2) provided for developing a short circuit between the base and emitter of an N-type IGBT during turn-OFF includes a P diffusion region (5), a P diffusion region (6), and a conductive film (10) and a second gate electr... | 07/04/2006 |
| 7067899 | Semiconductor integrated circuit device A semiconductor integrated circuit device according to the invention includes an N-type embedded diffusion region between a substrate and a first epitaxial layer in island regions serving as small signal section. The substrate and the first epitaxial layer are thus ... | 06/27/2006 |
| 7064359 | Switching semiconductor device and switching circuit A switching semiconductor device includes a first compound layer formed on a single crystal substrate which includes silicon carbide or sapphire, and including a general formula InxGa1-xN, where 0≦x≦1; a second compound layer formed on the ... | 06/20/2006 |
| 7026690 | Memory devices and electronic systems comprising integrated bipolar and FET devices The invention includes BIFETRAM devices. Such devices comprise a bipolar transistor in combination with a field effect transistor (FET) in a three-dimensional stacked configuration. The memory devices can be incorporated within semiconductor-on-insulator (SOI) const... | 04/11/2006 |
| 7022538 | Display device and manufacturing method for the same A screwdriver is disclosed having a shaft with a screw holder. The screw holder is receivable in a recess in a screw head, and has a spring element which can be elastically deformed transverse to the longitudinal axis of the shaft. A portion of the spring element ma... | 04/04/2006 |
| 6984593 | Beta control using a rapid thermal oxidation A method of forming semiconductor device treating a surface of a substrate to produce a discontinuous growth of a material on the surface through rapid thermal oxidation of the substrate surface at a temperature of less than about 700° C. ... | 01/10/2006 |
| 6972466 | Bipolar transistors with low base resistance for CMOS integrated circuits Complementary metal-oxide-semiconductor (CMOS) integrated circuits with bipolar transistors and methods for fabrication are provided. A bipolar transistor may have a lightly-doped base region. To reduce the resistance associated with making electrical contact to the... | 12/06/2005 |
| 6972442 | Efficiently fabricated bipolar transistor One embodiment is a method for fabricating the base of a bipolar transistor where the method comprises placing a first wafer in an undoped epi chamber. Next a first undoped base layer is grown over the first wafer. After growing the first undoped base layer, the fir... | 12/06/2005 |
| 6967406 | Semiconductor integrated circuit A layout method of a semiconductor integrated circuit is provided which improves characteristics of the circuit by giving hierarchical structure of interconnections regularity. A pair of emitter followers is disposed symmetrically with respect to a center line of a ... | 11/22/2005 |
| 6953981 | Semiconductor device with deep substrates contacts The present invention relates to a semiconductor device arranged at a surface of a semiconductor substrate having an initial doping having an electrical connection comprising at least one plug made of a material with a high conductivity, especially a material other ... | 10/11/2005 |
| 6914308 | Vertical PNP bipolar transistor A semiconductor device in which a vertical pnp-bipolar transistor is formed in a prescribed element region on a semiconductor substrate includes: a buried n+-layer of a high concentration formed in the prescribed element region; and a p-type collector lay... | 07/05/2005 |
| 6911715 | Bipolar transistors and methods of manufacturing the same A bipolar transistor in which the occurrence of Kirk effect is suppressed when a high current is injected into the bipolar transistor and a method of fabricating the bipolar transistor are described. The bipolar transistor includes a first collector region of a firs... | 06/28/2005 |
| 6911681 | Method of base formation in a BiCMOS process Disclosed is a bipolar complementary metal oxide semiconductor (BiCMOS) or NPN/PNP device that has a collector, an intrinsic base above the collector, shallow trench isolation regions adjacent the collector, a raised extrinsic base above the intrinsic base, a T-shap... | 06/28/2005 |
| 6864538 | Protection device against electrostatic discharges An ESD protection device encompassing a vertical bipolar transistor that is connected as a diode and has an additional displaced base area. The assemblage has a space-saving configuration and a decreased difference between snapback voltage and breakdown voltage.... | 03/08/2005 |
| 6847094 | Contact structure on a deep region formed in a semiconductor substrate The forming of a contact with a deep region of a first conductivity type formed in a silicon substrate. The contact includes a doped silicon well region of the first conductivity type and an intermediary region connected between the deep layer and the well. This int... | 01/25/2005 |
| 6838709 | Bipolar transistor A bipolar transistor includes the first group of transistors 610a, the second group of transistors 610b, the third group of transistors 610c and the fourth group of transistors 610d. The groups of transistors h... | 01/04/2005 |
| 6838745 | Semiconductor device having a separation structure for high withstand voltage An n-type well is formed in a p−-type semiconductor substrate and a p−-type epitaxial layer is formed on; the n-type well. An n−-type well is formed in the, p-type epitaxial layer on the n-type well so as to allow a RESURF oper... | 01/04/2005 |
| 6806550 | Evaluation configuration for semiconductor memories An evaluation configuration has a first MOS evaluation stage, an isolation stage, and a bipolar evaluation stage. The isolation stage is connected between the first MOS evaluation stage and the bipolar evaluation stage. The isolation stage isolates the first MOS eva... | 10/19/2004 |
| 6777781 | Base-to-substrate leakage cancellation The operating temperature range for a vertical PNP transistor can be extended by applying cancellation techniques. The vertical PNP generates a first leakage current from the base-collector region. Another vertical PNP transistor is configured to generate a second l... | 08/17/2004 |
