Did You Know...
...that Thomas Edison's patent application on his phonograph was approved by the Patent Office in just seven weeks? In contrast, it took Gordon Gould, the inventor of the laser, 30 years to obtain his patent -- finally awarded in 1988!
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 7411135 | Contour structures to highlight inspection regions An integrated circuit has a wiring layer below an insulator layer. A pad comprises a conductive material that is on the insulator layer. The pad has a wirebond connection region and a probe pad region. An inspection mark is between the wirebond connection region and... | 08/12/2008 |
| 7342293 | Bipolar junction transistors (BJTS) with second shallow trench isolation (STI) regions, and methods for forming same The present invention relates to bipolar junction transistors (BJTS). The collector region of each BJT is located in a semiconductor substrate surface and adjacent to a first shallow trench isolation (STI) region. A second STI region is provided, which extends betwe... | 03/11/2008 |
| 7304347 | Method for fabricating a power semiconductor device having a voltage sustaining layer with a terraced trench facilitating formation of floating islands A method is provided for forming a power semiconductor device. The method begins by providing a substrate of a first conductivity type and then forming a voltage sustaining region on the substrate. The voltage sustaining region is formed by depositing an epitaxial l... | 12/04/2007 |
| 7274104 | Semiconductor device having an interconnect that increases in impurity concentration as width increases The present invention provides a semiconductor device capable of suppressing an increase in electrical resistance of a narrow interconnect, while keeping reliability of a wide interconnect from being degraded. A semiconductor device comprises a plurality of intercon... | 09/25/2007 |
| 7192495 | Intermediate anneal for metal deposition The present teachings and illustrations describe a process for forming a plurality of conductive structures in or on a substrate. In one embodiment, the process comprises forming a plurality of recesses in or on the substrate, wherein the plurality of recesses inclu... | 03/20/2007 |
| 7176091 | Drain-extended MOS transistors and methods for making the same Drain-extended MOS transistors (T1, T2) and semiconductor devices (102) are described, as well as fabrication methods (202) therefor, in which a p-buried layer (130) is formed prior to formation of epitaxial silicon (106) ov... | 02/13/2007 |
| 7173320 | High performance lateral bipolar transistor A lateral bipolar transistor includes an emitter region, a base region, a collector region, and a gate disposed over the base region. A bias line is connected to the gate for applying a bias voltage thereto during operation of the transistor. The polarity of the bia... | 02/06/2007 |
| 7153774 | Method of making a semiconductor device that has copper damascene interconnects with enhanced electromigration reliability A method of making a semiconductor device is described. That method includes forming a copper containing layer on a substrate, and forming an alloying layer that includes an alloying element on the copper containing layer. After applying heat to cause an intermetall... | 12/26/2006 |
| 7148140 | Partial plate anneal plate process for deposition of conductive fill material A method of fabricating a semiconductor device is provided. An interlayer dielectric layer is formed on one or more semiconductor layers (402). One or more feature regions are formed in the interlayer dielectric layer (404). A first conductive layer is... | 12/12/2006 |
| 7126426 | Cascode amplifier structures including wide bandgap field effect transistor with field plates A multi-stage amplifier circuit arranged to take advantage of the desirable characteristics of non-field-plate and field plate transistors when amplifying a signal. One embodiment of a multi-stage amplifier according to the present invention comprises a non-field-pl... | 10/24/2006 |
| 7106120 | PCMO resistor trimmer Using programmable resistance material for a matching resistor, a resistor trimming circuit is designed to reversibly trim a matching resistor to match a reference resistor. The programmable resistance materials such as metal-amorphous silicon metal materials, phase... | 09/12/2006 |
| 7084455 | Power semiconductor device having a voltage sustaining region that includes terraced trench with continuous doped columns formed in an epitaxial layer A method is provided for forming a power semiconductor device. The method begins by providing a substrate of a first conductivity type and forming a voltage sustaining region on the substrate. The voltage sustaining region is formed in the following manner. First, a... | 08/01/2006 |
| 7067899 | Semiconductor integrated circuit device A semiconductor integrated circuit device according to the invention includes an N-type embedded diffusion region between a substrate and a first epitaxial layer in island regions serving as small signal section. The substrate and the first epitaxial layer are thus ... | 06/27/2006 |
| 6979625 | Copper interconnects with metal capping layer and selective copper alloys High reliable copper interconnects are formed with copper or a low resistivity copper alloy filling relatively narrow openings and partially filling relatively wider openings and a copper alloy having improved electromigration resistance selectively deposited in the... | 12/27/2005 |
| 6967406 | Semiconductor integrated circuit A layout method of a semiconductor integrated circuit is provided which improves characteristics of the circuit by giving hierarchical structure of interconnections regularity. A pair of emitter followers is disposed symmetrically with respect to a center line of a ... | 11/22/2005 |
| 6909164 | High performance vertical PNP transistor and method The invention includes a method and resulting structure for fabricating high performance vertical NPN and PNP transistors for use in BiCMOS devices. The resulting high performance vertical PNP transistor includes an emitter region including silicon and germanium, an... | 06/21/2005 |
| 6869854 | Diffused extrinsic base and method for fabrication The present invention provides a unique device structure and method that provides increased transistor performance in integrated bipolar circuit devices. The preferred embodiment of the present invention provides improved high speed performance by providing reduced ... | 03/22/2005 |
| 6856000 | Reduce 1/f noise in NPN transistors without degrading the properties of PNP transistors in integrated circuit technologies An interfacial oxide layer (185) is formed in the emitter regions of the NPN transistor (280, 220) and the PNP transistor (290, 200). Fluorine is selectively introduced into the polysilicon emitter region of the NPN transistor (220) to re... | 02/15/2005 |
| 6853048 | Bipolar transistor having an isolation structure located under the base, emitter and collector and a method of manufacture thereof The present invention provides a bipolar transistor and a method of manufacture thereof. The bipolar transistor includes a dielectric region located in a semiconductor substrate and a collector located in the semiconductor substrate and at least partially over the d... | 02/08/2005 |
| 6853017 | Bipolar transistor structure with ultra small polysilicon emitter A bipolar transistor structure includes trench isolation dielectric material formed in a semiconductor substrate to define a substrate active device region. A collector region is formed beneath the surface of the active device region. A base region is formed in the ... | 02/08/2005 |
| 6768183 | Semiconductor device having bipolar transistors An NPN bipolar transistor and a PNP bipolar transistor are formed in a semiconductor substrate. The NPN bipolar transistor has a p type emitter region, a p type collector region and an n type base region and is formed in an NPN forming region. The PNP bipolar transi... | 07/27/2004 |
| 6750528 | Bipolar device An integrated electronic device includes a semiconductor substrate layer having a major surface formed along a crystal plane. In one embodiment a first conductivity type region is formed in the substrate layer and a substantially monocrystalline semiconductor layer ... | 06/15/2004 |
| 6737722 | Lateral transistor having graded base region, semiconductor integrated circuit and fabrication method thereof The lateral pnp transistor encompasses a p-type semiconductor substrate, an n-type first buried region disposed on the semiconductor substrate, an n-type uniform base region disposed on the first buried region, an n-type first plug region disposed in the uniform bas... | 05/18/2004 |
| 6600199 | Deep trench-buried layer array and integrated device structures for noise isolation and latch up immunity The preferred embodiment of the present invention provides a buried layer that improves the latch up immunity of digital devices while providing isolation structures that provide noise isolation for both the digital and analog devices. The buried layer of... | 07/29/2003 |
| 6593628 | Semiconductor device and method of manufacturing same The invention relates to an essentially discrete semiconductor device comprising a semiconductor body (10) having a first, preferably bipolar, transistor (T1) with a first region (1) forming a collector (1) of T1, and a second, preferably also bipolar, tr... | 07/15/2003 |
| 6545337 | Semiconductor integrated circuit device Collector regions (32, 33) with films capable of withstanding high voltage by laminating 4 epitaxial layers when the collector regions (32, 33) are formed. In order to reduce effects caused by interference between the transistors (21, 22) and also reduce ... | 04/08/2003 |
| 6433402 | Selective copper alloy deposition Copper or a low resistivity copper alloy is initially deposited to fill relatively narrow openings leaving relatively wider openings unfilled. A copper alloy having improved electromigration resistance with respect to copper is then selectively deposited ... | 08/13/2002 |
| 6426667 | Bidirectional analog switch using two bipolar junction transistors which are both reverse connected or operating in the reverse or inverse mode The present invention relates to an integrated circuit bidirectional switch formed from bipolar transistor devices, in which the saturation voltage is sought to be reduced. More specifically, an integrated NPN bipolar transistor is formed with oxide insul... | 07/30/2002 |
| 6376880 | High-speed lateral bipolar device in SOI process A lateral bipolar transistor includes a semiconductor layer overlying an electrically insulating material and an insulating layer overlying a central portion of the semiconductor layer. A contact hole resides in the insulating layer and a conductive mater... | 04/23/2002 |
| 6262456 | Integrated circuit having transistors with different threshold voltages An ultra-large-scale integrated (ULSI) circuit includes MOSFETs which have different threshold voltages and yet have the same channel characteristics. The MOSFETs include gate structures with a polysilicon material. The polysilicon material is implanted w... | 07/17/2001 |
| 6124622 | MIS transistor with a three-layer device isolation film surrounding the MIS transistor A device isolation film is formed on one major surface of a semiconductor substrate so as to surround a device formation region. The device isolation film consists of a first layer made of silicon dioxide, a second layer made of polycrystalline silicon, a... | 09/26/2000 |
| 6049131 | Device formed by selective deposition of refractory metal of less than 300 Angstroms of thickness A method and the device produced by the method of selective refractory metal growth/deposition on exposed silicon, but not on the field oxide is disclosed. The method includes preconditioning a wafer in a DHF dip followed by the steps of 1) selectively de... | 04/11/2000 |
| 5915186 | Method of manufacturing heterojunction bipolar device having Si1-x Gex base In a semiconductor device manufacturing method for forming first and second bipolar transistors on a semiconductor substrate 1, a link base layer 5 for connecting a graft base layer (graft base layer 8) of the first bipolar transistor and an intrinsic bas... | 06/22/1999 |
| 5892264 | High frequency analog transistors, method of fabrication and circuit implementation A fabrication process for dielectrically isolated high frequency complementary analog bipolar and CMOS transistors. Polysilicon extrinsic bases, polysilicon emitters with sidewall spacers formed after intrinsic base formation provides high current gain, l... | 04/06/1999 |
| 5847440 | Bipolar transistor, semiconductor device having bipolar transistors An n-type epitaxial layer is formed on a main surface of a p-type silicon substrate. An n-type buried diffusion layer is formed extending in both the p-type silicon substrate and the n-type epitaxial layer. An n-type diffusion layer is formed in the surfa... | 12/08/1998 |
| 5729043 | Shallow trench isolation with self aligned PSG layer A method for forming trench isolation and in specific shallow trench isolation(STI) using SiO2 plugs is proposed. The SiO2 plugs of the STI have a buried phosphorus (P) rich layer introduced during and subsequent to the trench format... | 03/17/1998 |
| 5714793 | Complementary vertical bipolar junction transistors formed in silicon-on-saphire A method is described for fabricating a complementary, vertical bipolar sconducting structure. An N+ silicon island and a P+ silicon island separated by a first oxide layer are formed on a sapphire substrate. An NPN junction device is formed on the N+ si... | 02/03/1998 |
| 5670394 | Method of making bipolar transistor having amorphous silicon contact as emitter diffusion source The present invention teaches a method for fabricating a bipolar junction transistor ("BJT") from a semiconductor substrate having a base region, wherein the BJT comprises an increased Early voltage. The method initially comprises the step of forming a pa... | 09/23/1997 |
| 5641691 | Method for fabricating complementary vertical bipolar junction transistors in silicon-on-sapphire A method is described for fabricating a complementary, vertical bipolar semiconducting structure. An N+ silicon island and a P+ silicon island separated by a first oxide layer are formed on a sapphire substrate. An NPN junction device is formed on the N+ ... | 06/24/1997 |
| 5552626 | Semiconductor device having bipolar transistors with commonly interconnected collector regions A semiconductor device with bipolar transistors formed in respective island regions in which collector regions of the bipolar transistors do not need to be pulled up to the top of the corresponding island regions and do not need to be contacted with a col... | 09/03/1996 |
