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Method and apparatus for making a drink hop along a bar or counter
A method for generating a drink which appears to hop from a remote spot on the bar or counter and take one or more leaps, before landing in a patron's glass.
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| Number | Title | Issue Date |
| 8188567 | Semiconductor device and method for manufacturing A semiconductor and method for manufacturing a semiconductor device. In one embodiment the method includes providing a semiconductor substrate with a first substrate surface and at least one trench having at least one trench surface. The trench extends from the firs... | 05/29/2012 |
| 7982284 | Semiconductor component including an isolation structure and a contact to the substrate A semiconductor component includes a semiconductor body, in which are formed: a substrate of a first conduction type, a buried semiconductor layer of a second conduction type arranged on the substrate, and a functional unit semiconductor layer of a third conduction ... | 07/19/2011 |
| 7952162 | Semiconductor device and method for manufacturing the same A semiconductor device of one embodiment of the present invention includes a substrate; isolation layers, each of which is formed in a trench formed on the substrate and has an insulating film and a conductive layer; a semiconductor layer of a first conductivity typ... | 05/31/2011 |
| 7791163 | Semiconductor device and its manufacturing method In the process of manufacturing a semiconductor device, a first layer is formed on a substrate, and the first layer and the substrate are etched to form a trench. The inner wall of the trench is thermally oxidized. On the substrate, including inside the trench, is d... | 09/07/2010 |
| 7768096 | System for fabricating semiconductor components with conductive interconnects A system for fabricating semiconductor components includes a semiconductor substrate, a thinning system for thinning the semiconductor substrate, an etching system for forming the substrate opening, and a bonding system for bonding the conductive interconnect to the... | 08/03/2010 |
| 7723818 | Semiconductor devices and methods of manufacture thereof Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a semiconductor device includes a workpiece and a trench formed within the workpiece. The trench has an upper portion and a lower portion, the upper portion having a f... | 05/25/2010 |
| 7545020 | CMOS image sensor and method for manufacturing the same Embodiments relate to a CMOS image sensor. In embodiments, the CMOS image sensor may include a semiconductor substrate, a photodiode, a first conduction type impurity region, a first insulating layer, a conduction layer, and a second insulating layer. The semiconduc... | 06/09/2009 |
| 7429778 | Methods for forming wiring and electrode There is provided a method for forming wiring or an electrode by coating a substrate with a composition comprising (A) a complex of an amine compound and a hydrogenated aluminum compound and (B) a titanium compound or a composition comprising the complex and (C) met... | 09/30/2008 |
| 7420262 | Electronic component and semiconductor wafer, and method for producing the same The invention relates to an electronic component and a semiconductor wafer, and a method for producing them. The semiconductor wafer has strip-type separating regions. The separating regions are provided with through contacts in the direction of the rear side of the... | 09/02/2008 |
| 7420258 | Semiconductor device having trench structures and method In one embodiment, a pair of sidewall passivated trench contacts is formed in a substrate to provide electrical contact to a sub-surface feature. A doped region is diffused between the pair of sidewall passivated trenches to provide low resistance contacts. ... | 09/02/2008 |
| 7408224 | Vertical transistor structure for use in semiconductor device and method of forming the same According to some embodiments, a structure of vertical transistor includes gate electrodes distanced by a predetermined interval in an active region, formed in a vertical shape to have a predetermined depth from a top surface of a semiconductor substrate. A gate ins... | 08/05/2008 |
| 7393770 | Backside method for fabricating semiconductor components with conductive interconnects A backside method for fabricating a semiconductor component with a conductive interconnect includes the step of providing a semiconductor substrate having a circuit side, a backside, and a substrate contact on the circuit side. The method also includes the steps of ... | 07/01/2008 |
| 7385275 | Shallow trench isolation method for shielding trapped charge in a semiconductor device A semiconductor structure and associated method for forming the semiconductor structure. The semiconductor structure comprises a first field effect transistor (FET), a second FET, and a shallow trench isolation (STI) structure. The first FET comprises a channel regi... | 06/10/2008 |
| 7382015 | Semiconductor device including an element isolation portion having a recess A non-volatile semiconductor memory device, which is intended to prevent data destruction by movements of electric charges between floating gates and thereby improve the reliability, includes element isolation/insulation films buried into a silicon substrate to isol... | 06/03/2008 |
| 7354699 | Method for producing alignment mark A method for producing an alignment mark is performed such that the alignment mark can be removed from the surface of a substrate without leaving any trace thereof after the alignment mark has been used for alignment. After a first photoresist layer has been formed ... | 04/08/2008 |
| 7335946 | Structures of and methods of fabricating trench-gated MIS devices In a trench-gated MIS device contact is made to the gate within the trench, thereby eliminating the need to have the gate material, typically polysilicon, extend outside of the trench. This avoids the problem of stress at the upper corners of the trench. Contact bet... | 02/26/2008 |
| 7332772 | Semiconductor device having a recessed gate and asymmetric dopant regions and method of manufacturing the same A semiconductor device, having a recessed gate and asymmetric dopant regions, comprises a semiconductor substrate having a trench with a first sidewall and a second sidewall, the heights of which are different from each other, a gate insulating layer pattern dispose... | 02/19/2008 |
| 7319271 | Semiconductor device Disclosed herein is a semiconductor device having a multi-layer wiring structure includes a plurality of wiring layers laminated on a substrate, the wiring layers each including a buried wiring and a via formed by filling with a conductive material the inside of a w... | 01/15/2008 |
| 7314798 | Method of fabricating a nonvolatile storage array with continuous control gate employing hot carrier injection programming A method of making an array of storage cells includes a first source/drain region underlying a first trench defined in a semiconductor substrate and a second source/drain region underlying a second trench in the substrate. A charge storage stack lines each of the tr... | 01/01/2008 |
| 7294901 | Semiconductor device with improved resurf features including trench isolation structure A p impurity region (3) defines a RESURF isolation region in an n− semiconductor layer (2). A trench isolation structure (8a) and the p impurity region (3) together define a trench isolation region in the n− | 11/13/2007 |
| 7282779 | Device, method of manufacture thereof, manufacturing method for active matrix substrate, electro-optical apparatus and electronic apparatus A device includes banks formed on a substrate, a conducting film formed by droplet ejection onto a predetermined pattern formation region in a groove between the banks, and a second conductive film formed by droplet ejection disposed outside the pattern formation re... | 10/16/2007 |
| 7279770 | Isolation techniques for reducing dark current in CMOS image sensors A structure for isolating areas in a semiconductor device is provided. The structure includes a trench having first and second portions formed in a substrate. The first portion has a first width, and the second portion has a second width and is below the first porti... | 10/09/2007 |
| 7274074 | Semiconductor integrated circuit device Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections ... | 09/25/2007 |
| 7259442 | Selectively doped trench device isolation A selectively doped trench isolation device is provided. The trench isolation device of the preferred embodiment includes a semiconductor substrate having a trench. A thin field oxide layer is grown on the side walls of the trench, and the trench is filled with a he... | 08/21/2007 |
| 7230312 | Transistor having vertical junction edge and method of manufacturing the same Techniques for forming devices, such as transistors, having vertical junction edges. More specifically, shallow trenches are formed in a substrate and filled with an oxide. Cavities may be formed in the oxide and filled with a conductive material, such a heavily dop... | 06/12/2007 |
| 7211448 | Semiconductor device manufacturing method capable of reliable inspection for hole opening and semiconductor devices manufactured by method A substrate defining an insulating surface layer portion and formed with a wiring groove filled with a wiring line the wiring line is electrically connected to a conductive member. The conductive member occupies an area larger than an area of the wiring line as view... | 05/01/2007 |
| 7180159 | Bipolar transistor having base over buried insulating and polycrystalline regions A bipolar transistor in a monocrystalline semiconductor substrate (101), which has a first conductivity type and includes a surface layer (102) of the opposite conductivity type. The transistor comprises an emitter contact (110) on the surface l... | 02/20/2007 |
| 7166891 | Semiconductor device with etch resistant electrical insulation layer between gate electrode and source electrode A trench-structure semiconductor device is highly reliable and has an increased resistance to hydrofluoric acid cleaning or other cleaning of an insulation film between a gate electrode, which is embedded in a trench, and source electrode. In a trench-structure semi... | 01/23/2007 |
| 7161225 | Reducing shunts in memories with phase-change material A memory cell may include a phase-change material. Adhesion between the phase-change material and a dielectric or other substrate may be enhanced by using an adhesion enhancing interfacial layer. Conduction past the phase-change material through the interfacial laye... | 01/09/2007 |
| 7154159 | Trench isolation structure and method of forming the same A trench isolation structure and a method of forming a trench isolation structure are provided. The method includes providing a substrate having a trench. A polysilicon liner is formed in the trench. A dielectric layer, such as spin-on glass, is formed in the trench... | 12/26/2006 |
| 7151314 | Semiconductor device with superimposed poly-silicon plugs A semiconductor device includes a first insulating layer; a first poly-silicon plug formed in the first insulating layer; a second insulating layer, formed on the first insulating layer; and a second poly-silicon plug that is formed in the second insulating layer. A... | 12/19/2006 |
| 7144804 | Semiconductor device and method of manufacturing the same A semiconductor device comprises a semiconductor substrate, an interlayer insulating film including a first insulating film formed above the substrate and having a relative dielectric constant smaller than 2.5 and a second insulating film formed to cover the first i... | 12/05/2006 |
| 7141478 | Multi-stage EPI process for forming semiconductor devices, and resulting device The present invention is generally directed to a multi-stage epi process for forming semiconductor devices, and the resulting device. In one illustrative embodiment, the method comprises forming a first layer of epitaxial silicon above a surface of a semiconducting ... | 11/28/2006 |
| 7115973 | Dual-sided semiconductor device with a resistive element that requires little silicon surface area A dual-sided semiconductor device is formed on a wafer with a resistive element that is formed through the wafer. By forming the resistive element through the wafer, a resistive element, such as a large resistive element, can be formed on the wafer that requires ver... | 10/03/2006 |
| 7115964 | Manufacturing method for SOI semiconductor device, and SOI semiconductor device A manufacturing method for an SOI semiconductor device includes creating transistors and an element isolation region on a semiconductor layer in an SOI substrate. The method also includes covering the transistors and the element isolation region with a first insulat... | 10/03/2006 |
| 7095119 | Semiconductor device A semiconductor device is equipped with fuses each made of a conductive material vertically extended through an insulator layer employed in the semiconductor device. Holes are formed which vertically penetrate the insulator layer. Sidewalls are formed on their corre... | 08/22/2006 |
| 7078814 | Method of forming a semiconductor device having air gaps and the structure so formed A method of forming a semiconductor device, and the device so formed. Depositing alternating layers of a first and a second dielectric material, wherein the first and second dielectric materials are selectively etchable at different rates. Forming a first feature wi... | 07/18/2006 |
| 7061032 | Semiconductor device with upper portion of plugs contacting source and drain regions being a first self-aligned silicide A semiconductor device including: a cell transistor including: a pair of source and drain regions formed in a surface portion of a silicon substrate so as to have a predetermined space therebetween; a channel region sandwiched by the source and drain regions; a gate... | 06/13/2006 |
| 7053463 | High-voltage integrated vertical resistor and manufacturing process thereof The manufacturing process comprises the steps of growing epitaxially a first layer from a semiconductor material substrate, forming in the first layer a first and a second buried region spaced from one another and having conductivity of the type opposite that of the... | 05/30/2006 |
| 7045857 | Termination for trench MIS device having implanted drain-drift region A trench MIS device is formed in a P-epitaxial layer that overlies an N-epitaxial layer and an N+ substrate. In one embodiment, the device includes an N-type drain-drift region that extends from the bottom of the trench to the N-epitaxial layer. Preferably, the drai... | 05/16/2006 |
