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| Number | Title | Issue Date |
| 8115273 | Deep trench isolation structures in integrated semiconductor devices A integrated semiconductor device has a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type over the first layer, a third semiconductor layer of a second conductivity type over the second layer, an isol... | 02/14/2012 |
| 7443007 | Trench isolation structure having an implanted buffer layer The present invention provides a trench isolation structure, a method of manufacture therefor and a method for manufacturing an integrated circuit including the same. The trench isolation structure (130), in one embodiment, includes a trench located within a ... | 10/28/2008 |
| 7425752 | Semiconductor device channel termination A semiconductor device has a channel termination region for using a trench (30) filled with field oxide (32) and a channel stopper ring (18) which extends from the first major surface (8) through p-well (6) along the outer edge ( | 09/16/2008 |
| 7382015 | Semiconductor device including an element isolation portion having a recess A non-volatile semiconductor memory device, which is intended to prevent data destruction by movements of electric charges between floating gates and thereby improve the reliability, includes element isolation/insulation films buried into a silicon substrate to isol... | 06/03/2008 |
| 7365400 | Semiconductor device and method for manufacturing the same A method for manufacturing semiconductor device employs an EXTIGATE structure. In accordance with the method, a predetermined thickness of the device isolation film is etched to form a recess. The recess is then filled with a second nitride film. A stacked structure... | 04/29/2008 |
| 7358149 | Substrate isolation in integrated circuits Substrate isolation trench (224) are formed in a semiconductor substrate (120). Dopant (e.g. boron) is implanted into the trench sidewalls by ion implantation to suppress the current leakage along the sidewalls. During the ion implantation, the transis... | 04/15/2008 |
| 7329953 | Structure for reducing leakage currents and high contact resistance for embedded memory and method for making same A method for fabricating an insulating layer having contact openings of varying depths for logic/DRAM circuits is achieved using a single mask and etch step. After forming stacked or trench capacitors, a planar insulating layer is formed. Contact openings are etched... | 02/12/2008 |
| 7304354 | Buried guard ring and radiation hardened isolation structures and fabrication methods Semiconductor devices can be fabricated using conventional designs and process but including specialized structures to reduce or eliminate detrimental effects caused by various forms of radiation. Such semiconductor devices can include the one or more parasitic isol... | 12/04/2007 |
| 7300834 | Methods of forming wells in semiconductor devices Disclosed herein are methods of forming a well in a semiconductor device, in which a well end point under a trench is formed deeper than other area by well implantation prior to trench filling and by which leakage current is minimized. In one example, the disclosed ... | 11/27/2007 |
| 7294903 | Transistor assemblies Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry are described. In one embodiment, active areas are formed over a substrate, with one of the ... | 11/13/2007 |
| 7271468 | High-voltage compatible, full-depleted CCD A charge coupled device for detecting electromagnetic and particle radiation is described. The device includes a high-resistivity semiconductor substrate, buried channel regions, gate electrode circuitry, and amplifier circuitry. For good spatial resolution and high... | 09/18/2007 |
| 7253047 | Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry are described. In one embodiment, active areas are formed over a substrate, with one of the ... | 08/07/2007 |
| 7236001 | Redundancy circuits hardened against single event upsets A decision block is incorporated into a circuit design to provide hardening against single event upset and to store data. The decision block includes a storage element that stores data as long as inputs to the decision block remain constant. The decision block recei... | 06/26/2007 |
| 7221035 | Semiconductor structure avoiding poly stringer formation The present invention discloses a semiconductor structure avoiding the poly stringer formation in semiconductor processing. A semiconductor device is divided into a memory cell area and a peripheral portion. A plurality of parallel first isolation devices are positi... | 05/22/2007 |
| 7180109 | Field effect transistor and method of fabrication The present invention is a novel field effect transistor having a channel region formed from a narrow bandgap semiconductor film formed on an insulating substrate. A gate dielectric layer is formed on the narrow bandgap semiconductor film. A gate electrode is then f... | 02/20/2007 |
| 7173339 | Semiconductor device having a substrate an undoped silicon oxide structure and an overlaying doped silicon oxide structure with a sidewall terminating at the undoped silicon oxide structure An etchant including C2HxFy, where x is an integer from two to five, inclusive, where y is an integer from one to four, inclusive, and where x plus y equals six, etches doped silicon dioxide with selectivity over both undoped silicon... | 02/06/2007 |
| 7170147 | Dissipative isolation frames for active microelectronic devices, and methods of making such dissipative isolation frames Microelectronic apparatus having protection against high frequency crosstalk radiation, comprising: a planar insulating substrate; an active semiconductor electronic device located over a first region of the insulating substrate; and a doped semiconductor located in... | 01/30/2007 |
| 7166906 | Package with barrier wall and method for manufacturing the same A ball grid array (BGA) package that may suppress flash contamination may include a flash contamination barrier wall. The barrier wall may be a portion of a copper pattern provided on a substrate. During a molding process, the flash contamination barrier may prevent... | 01/23/2007 |
| 7157754 | Solid-state imaging device and interline transfer CCD image sensor A high-performance solid-state imaging device is provided. The solid-state imaging device includes: a plurality of pixel cells; and a driving unit. Each of the plurality of pixel cells includes: a photodiode that converts incident light into a signal charge and stor... | 01/02/2007 |
| 7071515 | Narrow width effect improvement with photoresist plug process and STI corner ion implantation A method to reduce the inverse narrow width effect in NMOS transistors is described. An oxide liner is deposited in a shallow trench that is formed to isolate active areas in a substrate. A photoresist plug is formed in the shallow trench and is recessed below the t... | 07/04/2006 |
| 7071531 | Trench isolation for semiconductor devices A method of fabricating an integrated circuit includes forming an isolation trench in a semiconductor substrate and partially filling the trench with a dielectric material so that at least the sidewalls of the trench are coated with the dielectric material. Ions are... | 07/04/2006 |
| 7064087 | Phosphorous-doped silicon dioxide process to customize contact etch profiles A method for depositing a doped silicon dioxide layer is provided that allows the dopant concentration in the silicon dioxide layer to be controlled throughout the layer. By controlling the dopant concentration throughout the layer the etch profile of contact holes ... | 06/20/2006 |
| 7053459 | Semiconductor integrated circuit device and process for producing the same Formation of an WNx film 24 constituting a barrier layer of a gate electrode 7A having a polymetal structure is effected in an atmosphere containing a high concentration nitrogen gas, whereby release of N (nitrogen) from the WNx f... | 05/30/2006 |
| 7045436 | Method to engineer the inverse narrow width effect (INWE) in CMOS technology using shallow trench isolation (STI) A method (200) of forming an isolation structure is disclosed, and includes forming an isolation trench in a semiconductor body (214) associated with an isolation region, and filling a bottom portion of the isolation trench with an implant masking mate... | 05/16/2006 |
| 7029997 | Method of doping sidewall of isolation trench A method of doping sidewalls of an isolation trench is provided. A substrate having a trench thereon is provided. A blocking layer is formed within the trench such that the top surface of the blocking layer is lower than the top surface of the substrate. A sidewall ... | 04/18/2006 |
| 7019379 | Semiconductor device comprising voltage regulator element A semiconductor device includes a heavily doped layer 25 of p-type formed in the surface of an n-type well 21, an intermediately doped layer 26 of p-type formed to adjoin and surround the heavily p-doped layer 25, and an isolation region ... | 03/28/2006 |
| 7012309 | High-voltage integrated CMOS circuit The invention relates to an integrated CMOS circuit comprising, in a semiconductor substrate (1) with a first type of conductivity, a casing (2) of a second type of retrograde-doped conductivity, the end of said casing being covered by an inter-casing ... | 03/14/2006 |
| 7009271 | Memory device with an alternating Vss interconnection A semiconductor memory device provides non-volatile memory with a memory array having an alternating Vss interconnection. Using the alternating Vss interconnection, a low implant dosage is added to a region proximate to the lower areas of an STI region, such as bene... | 03/07/2006 |
| 6960818 | Recessed shallow trench isolation structure nitride liner and method for making same A method for reducing hot carrier reliability problems within an integrated circuit device. The method includes forming a shallow trench isolation structure incorporated with the device by filling a trench with a photoresist plug and removing a portion of the photor... | 11/01/2005 |
| 6958521 | Shallow trench isolation structure Method for preventing sneakage in shallow trench isolation and STI structure thereof. A semiconductor substrate having a pad layer and a trench formed thereon is provided, followed by the formation of a doped first lining layer on the sidewall of the trench. A secon... | 10/25/2005 |
| 6953961 | DRAM structure and fabricating method thereof A dynamic random access memory (DRAM) structure and a fabricating process thereof are provided. In the fabricating process, a channel region is formed with a doped region having identical conductivity as the substrate in a section adjacent to an isolation structure.... | 10/11/2005 |
| 6940145 | Termination structure for a semiconductor device A semiconductor device (e.g. MOSFET or IGBT) comprises active and termination regions (1,2) formed in a semiconductor substrate (4). The substrate (4) has an upper surface and a termination including a trench (12) extending into the subst... | 09/06/2005 |
| 6939773 | Semiconductor devices and manufacturing methods thereof Semiconductor device fabrication methods include forming an oxide layer on a semiconductor substrate, forming an arrangement trench on the semiconductor substrate by patterning the oxide layer and the semiconductor substrate, forming a nitride layer on the arrangeme... | 09/06/2005 |
| 6921705 | Method for forming isolation layer of semiconductor device A method for forming an isolation layer of a semiconductor device. The method includes: a) sequentially laminating a pad oxide layer and pad nitride layer on a semiconductor substrate; b) selectively removing the pad nitride layer, selectively removing the pad oxide... | 07/26/2005 |
| 6897112 | Method for fabricating an integrated semiconductor configuration with the aid of thermal oxidation, related semiconductor configuration, and related memory unit A method for fabricating an integrated semiconductor configuration includes generating a polycrystalline layer at a surface of a base layer and doping the polycrystalline layer. An oxide layer is generated at the polycrystalline layer by rapid thermal oxidation so t... | 05/24/2005 |
| 6894354 | Trench isolated transistors, trench isolation structures, memory cells, and DRAMs An isolation trench in a semiconductor includes a first isolation trench portion having a first depth and having a first sidewall intersecting a surface of the semiconductor at a first angle. A second isolation trench portion extends within and below the first isola... | 05/17/2005 |
| 6856001 | Trench isolation for semiconductor devices A method of fabricating an integrated circuit includes forming an isolation trench in a semiconductor substrate and partially filling the trench with a dielectric material so that at least the sidewalls of the trench are coated with the dielectric material. Ions are... | 02/15/2005 |
| 6849519 | Method of forming an isolation layer in a semiconductor devices A method of forming an isolation layer in semiconductor devices is disclosed. The method includes forming the isolating film by means of a method in which a method of forming a V-type trench at the isolation region, implanting ions capable of accelerating oxidizatio... | 02/01/2005 |
| 6815714 | Conductive structure in a semiconductor material A conductive structure provides a conductive path from a first region in a semiconductor material to a second spaced apart region in the semiconductor material by forming one or more trenches between the first and second regions, and implanting a dopant into the bot... | 11/09/2004 |
| 6812486 | Conductive structure and method of forming the structure A conductive structure provides a conductive path from a first region in a semiconductor material to a second spaced apart region in the semiconductor material by forming a plurality of trenches between the first and second regions, implanting a dopant into the bott... | 11/02/2004 |
