Quotables
"There is practically no chance communications space satellites will be used to provide better telephone, telegraph, television, or radio service inside the United States."
T. Craven, FCC Commissioner ; 1961
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 7439558 | Method and system for controlled oxygen incorporation in compound semiconductor films for device performance enhancement A method and system for providing a bipolar transistor is described. The method and system include providing a compound base region, providing an emitter region coupled with the compound base region, and providing a collector region coupled with the compound base re... | 10/21/2008 |
| 7342293 | Bipolar junction transistors (BJTS) with second shallow trench isolation (STI) regions, and methods for forming same The present invention relates to bipolar junction transistors (BJTS). The collector region of each BJT is located in a semiconductor substrate surface and adjacent to a first shallow trench isolation (STI) region. A second STI region is provided, which extends betwe... | 03/11/2008 |
| 7192838 | Method of producing complementary SiGe bipolar transistors Method of producing complementary SiGe bipolar transistors. In a method of producing complementary SiGe bipolar transistors, interface oxide layers (38, 58) for NPN and PNP emitters (44, 64), are separately formed and emitter polysilicon (40, 60... | 03/20/2007 |
| 7187035 | Semiconductor device comprising multiple layers with trenches formed on a semiconductor substrate A method of manufacturing a semiconductor device substrate is disclosed, which comprises forming a mask layer patterned on a semiconductor layer insulated from a surface of a semiconductor substrate by an electrically insulating layer, etching the semiconductor laye... | 03/06/2007 |
| 7026690 | Memory devices and electronic systems comprising integrated bipolar and FET devices The invention includes BIFETRAM devices. Such devices comprise a bipolar transistor in combination with a field effect transistor (FET) in a three-dimensional stacked configuration. The memory devices can be incorporated within semiconductor-on-insulator (SOI) const... | 04/11/2006 |
| 7012330 | Integrated circuit device having I/O structures with reduced input loss The present invention is an input/output (I/O) structure for an integrated circuit device which increases the input signal energy transfer characteristic and allows for increased operating frequency of the device. The I/O structure includes a conductive region in a ... | 03/14/2006 |
| 7002221 | Bipolar transistor having raised extrinsic base with selectable self-alignment and methods of forming same A bipolar transistor with raised extrinsic base and selectable self-alignment between the extrinsic base and the emitter is disclosed. The fabrication method may include the formation of a predefined thickness of a first extrinsic base layer of polysilicon or silico... | 02/21/2006 |
| 6879021 | Electronically programmable antifuse and circuits made therewith An antifuse device (120) that includes a bias element (124) and an programmable antifuse element (128) arranged in series with one another so as to form a voltage divider having an output node (F) located between the bias and antifuse elements. ... | 04/12/2005 |
| 6856000 | Reduce 1/f noise in NPN transistors without degrading the properties of PNP transistors in integrated circuit technologies An interfacial oxide layer (185) is formed in the emitter regions of the NPN transistor (280, 220) and the PNP transistor (290, 200). Fluorine is selectively introduced into the polysilicon emitter region of the NPN transistor (220) to re... | 02/15/2005 |
| 6828650 | Bipolar junction transistor structure with improved current gain characteristics A Bipolar Junction Transistor (BJT) that reduces the variation in the current gain through the use of a trench pullback structure. The trench pullback structure is comprised of a trench and an active region. The trench reduces recombination in the emitter-base regio... | 12/07/2004 |
| 6690083 | Use of silicide blocking layer to create high valued resistor and diode for sub-1V bandgap The present invention is drawn to a method and a system for creating a sub-1V bandgap reference (BGR) circuit. In particular, a sub-1V BGR circuit is formed comprising a shallow trench isolation (STI) region and a poly silicon region above said STI region... | 02/10/2004 |
| 6646320 | Method of forming contact to poly-filled trench isolation region Existing polysilicon emitter technology is used to contact poly fill in a trench isolation structure. A standard single poly emitter window process is followed. An "emitter window" is masked directly over the polysilicon trench fill. Heavily doped single ... | 11/11/2003 |
| 6534820 | Integrated dynamic memory cell having a small area of extent, and a method for its production An integrated dynamic memory cell having a small area of extent on a semiconductor substrate is described. The memory cell has a selection MOSFET with a gate connection area that is connected to a word line, a source connection doping area which is connec... | 03/18/2003 |
| 6525403 | Semiconductor device having MIS field effect transistors or three-dimensional structure A semiconductor projection is formed on a semiconductor substrate of the first conductivity type and has a semiconductor layer of the first conductivity type. The semiconductor projection has a top surface and side surfaces. A gate electrode is formed abo... | 02/25/2003 |
| 6495897 | Integrated circuit having etch-resistant layer substantially covering shallow trench regions An integrated circuit is fabricated with a layer of polysilicon located on top of shallow trench regions. The polysilicon is patterned so that the trench features are not exposed during an etching operation performed on the polysilicon layer. The process ... | 12/17/2002 |
| 6433387 | Lateral bipolar transistor Lateral bipolar transistor, in which a thin diffusion barrier (4) is applied to a base region (10) between an emitter region (9) and a collector region (11), and there is present, on said barrier, a base electrode (8) which is provided for low-resistance ... | 08/13/2002 |
| 6376880 | High-speed lateral bipolar device in SOI process A lateral bipolar transistor includes a semiconductor layer overlying an electrically insulating material and an insulating layer overlying a central portion of the semiconductor layer. A contact hole resides in the insulating layer and a conductive mater... | 04/23/2002 |
| 6329699 | Bipolar transistor with trenched-groove isolation regions The invention relates to semiconductor devices having a bipolar transistor to form an isolation area within a base electrode contact area to ensure stable contact of the base electrode. The bipolar transistor formed in the transistor area is in the form o... | 12/11/2001 |
| 6093953 | Isolation regions and methods of forming isolation regions A silicon-comprising layer is employed adjacent a trench during planarization of an oxide fill within the trench. An overhanging oxide sidewall is formed along a lateral edge of a trenched isolation region, the overhanging oxide sidewall overlapping an up... | 07/25/2000 |
| 6073343 | Method of providing a variable guard ring width between detectors on a substrate A method is provided for maximizing substrate usage in the fabrication of flat panel displays or detectors, while also maximizing electrostatic protection for the displays or detectors. Initially, at least two detectors are positioned on the substrate, wi... | 06/13/2000 |
| 6005284 | Semiconductor device and its manufacturing method A bipolar semiconductor device includes an npn transistor using a base outlet electrode in the form of a polycrystalline Si film and one or more other devices using an electrode in the form of a polycrystalline Si film supported on a common p-type Si subs... | 12/21/1999 |
| 5998816 | Sensor element with removal resistance region A sensor element provided with a silicon substrate having a semiconductor circuit, a sensing-element portion formed on the silicon substrate and connected to the semiconductor circuit, and a cavity portion formed by removing a silicon substrate portion be... | 12/07/1999 |
| 5982021 | Vertical polysilicon diode compatible with CMOS/BiCMOS integrated circuit processes A junction diode structure formed within an integrated circuit. The junction diode structure comprises a semiconductor substrate. The junction diode structure also comprises a dielectric layer formed over the semiconductor substrate. In addition, the junc... | 11/09/1999 |
| 5914523 | Semiconductor device trench isolation structure with polysilicon bias voltage contact A semiconductor device, polysilicon-contacted trench isolation- structure that provides improved electrical isolation stability, a method of operating a polysilicon-contacted trench isolated semiconductor device, and a process for manufacturing a polysili... | 06/22/1999 |
| 5910676 | Method for forming a thick base oxide in a BiCMOS process A BiCMOS structure and a method for making the same is disclosed, where the dielectric layer between the emitter electrode and the base region is formed of a deposited dielectric. After definition of the bipolar and MOS moat regions, a layer of polysilico... | 06/08/1999 |
| 5909623 | Manufacturing method of semiconductor device A manufacturing method of the present invention comprises the first step of forming an epitaxial base layer in an opening of an element-isolating oxide film on a semiconductor substrate in a non-selection condition, the second step of growing a silicon ox... | 06/01/1999 |
| 5877539 | Bipolar transistor with a reduced collector series resistance A collector structure in a bipolar transistor on a semiconductor substrate is surrounded by trench isolations. A well region has a first impurity concentration and extends in an upper portion of the semiconductor substrate surrounded by the trench isolati... | 03/02/1999 |
| 5861659 | Semiconductor device In a semiconductor device having regions of a vertical pnp bipolar transistor, that is, a collector region composed of a p-type semiconductor region, a base region composed of an n-type semiconductor region and an emitter region composed of a p-type semic... | 01/19/1999 |
| 5856228 | Manufacturing method for making bipolar device having double polysilicon structure A semiconductor device and a manufacturing method therefor which can simultaneously realize both a reduction in base transit time by a reduction in base width and a reduction in base resistance by a reduction in link base resistance. The semiconductor dev... | 01/05/1999 |
| 5856700 | Semiconductor device with doped semiconductor and dielectric trench sidewall layers The present invention is directed to a semiconductor device having an ohmic contact to a buried layer. The device includes a device wafer having on its first surface a first dielectric layer and on its second surface a doped epitaxial layer that comprises... | 01/05/1999 |
| 5854503 | Maximization of low dielectric constant material between interconnect traces of a semiconductor circuit A structure and method of maximizing the volume of low dielectric constant material between adjacent traces of a conductive interconnect structure. A semiconductor structure includes a semiconductor substrate, a first insulating layer located over the sem... | 12/29/1998 |
| 5847438 | Bonded IC substrate with a high breakdown voltage and large current capabilities A semiconductor device includes a groove formed in a surface of a first semiconductor substrate of one conductivity type in order to partition and isolate first and second device regions. A first insulating film on the first semiconductor substrate of the... | 12/08/1998 |
| 5834800 | Heterojunction bipolar transistor having mono crystalline SiGe intrinsic base and polycrystalline SiGe and Si extrinsic base regions A heterojunction bipolar transistor in an integrated circuit has intrinsic and extrinsic base portions. The intrinsic base portion substantially comprises epitaxial silicon-germanium alloy. The extrinsic base portion substantially comprises polycrystallin... | 11/10/1998 |
| 5763932 | Isolation regions and methods of forming isolation regions A silicon-comprising layer is employed adjacent a trench during planarization of an oxide fill within the trench. An overhanging oxide sidewall is formed along a lateral edge of a trenched isolation region, the overhanging oxide sidewall overlapping an up... | 06/09/1998 |
| 5733791 | Methods for fabrication of bipolar device having high ratio of emitter to base area A bipolar transistor is provided whose emitter surrounds the base. The transistor has in some embodiments a high ratio of the emitter area to the base area and low collector and emitter resistances. Further, a transistor is provided in which a collector c... | 03/31/1998 |
| 5604374 | Semiconductor device and manufacturing method thereof A semiconductor device comprises a semiconductor substrate having a main surface, a first semiconductor region of a first conductive type, formed on the main surface of the semiconductor substrate, a surrounding of the first semiconductor region is buried... | 02/18/1997 |
| 5581112 | Lateral bipolar transistor having buried base contact A lateral bipolar transistor comprising a self-aligned polysilicon base contact, and polysilicon emitter and collector contacts is provided. The self-aligned base contact significantly reduces the base width and therefore the base resistance compared with... | 12/03/1996 |
| 5548155 | Bipolar type semiconductor device having small parasitic capacitance, small dimensions, and small variation in transistor characteristics A semiconductor device in which a bipolar transistor is provided, such as a BiCMOS, and a production process thereof. The device has collector region of a first conductivity type; an intrinsic base region of a second conductivity type provided on the coll... | 08/20/1996 |
| 5541124 | Method for making bipolar transistor having double polysilicon structure A semiconductor device and a manufacturing method therefor which can simultaneously realize both a reduction in base transit time by a reduction in base width and a reduction in base resistance by a reduction in link base resistance. The semiconductor dev... | 07/30/1996 |
| 5506157 | Method for fabricating pillar bipolar transistor Disclosed is a pillar bipolar transistor which has a bidirectional operation characteristic and in which a parasitic junction capacitance of a base electrode, and a method for fabricating the transistor comprises etching a substrate using a first patterne... | 04/09/1996 |
