Did You Know...
...that two musicians were responsible for the invention of color print film? Fascinated by photography, Leopold Godowsky and Leopold Mannes worked together to produce an easy-to-use, practical color film. They worked full time as music teachers and gave concerts while experimenting during their off hours in Mannes' kitchen. Their success earned them full-time, well-paying jobs at Kodak and their efforts resulted in Kodachrome film, which was introduced in 1935.
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| Number | Title | Issue Date |
| 7902630 | Isolated bipolar transistor An isolated bipolar transistor formed in a P-type semiconductor substrate includes an N-type submerged floor isolation region and a filled trench extending downward from the surface of the substrate to the floor isolation region. Together the floor isolation region ... | 03/08/2011 |
| 7872326 | Array of vertical bipolar junction transistors, in particular selectors in a phase change memory device A process for manufacturing an array of bipolar transistors, wherein deep field insulation regions of dielectric material are formed in a semiconductor body, thereby defining a plurality of active areas, insulated from each other and a plurality of bipolar transisto... | 01/18/2011 |
| 7759764 | Elevated bipolar transistor structure A semiconductor structure includes a substrate; an isolation structure in the substrate, wherein the isolation structure defines a region therein; a first semiconductor region having at least a portion in the region defined by the isolation structure, wherein the fi... | 07/20/2010 |
| 7521772 | Monocrystalline extrinsic base and emitter heterojunction bipolar transistor and related methods A heterostructure bipolar transistor (HBT) and related methods are disclosed. In one embodiment, the HBT includes a heterostructure bipolar transistor (HBT) including: a substrate; a monocrystalline emitter atop the substrate; a collector in the substrate; at least ... | 04/21/2009 |
| 7498654 | Transistor apparatus A transistor apparatus includes a silicon substrate and a barrier structure extending substantially from generally adjacent the silicon substrate to a locus displaced from the silicon substrate. The barrier structure generally surrounds a volume containing connectio... | 03/03/2009 |
| 7420228 | Bipolar transistor comprising carbon-doped semiconductor A bipolar transistor comprising a collector region of a first conduction type, and a subcollector region of the first conduction type at a first side of the collector region. The transistor further includes a base region of the second conduction type provided at a s... | 09/02/2008 |
| 7358545 | Bipolar junction transistor A bipolar junction transistor is provided. A p-type well region surrounds an n-type emitter and connects with the bottom of the emitter to serve as a base. A p-type base pick-up region connects with the base and surrounds the emitter. An n-type deep well, connected ... | 04/15/2008 |
| 7354840 | Method for opto-electronic integration on a SOI substrate According to an exemplary embodiment, a method includes providing a silicon-on-insulator substrate including a buried oxide layer situated over a bulk silicon substrate and a silicon layer situated over the buried oxide layer. A trench is formed in the silicon layer... | 04/08/2008 |
| 7348233 | Methods for fabricating a CMOS device including silicide contacts Methods are provided for fabricating a CMOS device having a silicon substrate including a first N-type region and a second P-type region. The method includes the steps of forming a first gate electrode overlying the first N-type region and a second gate electrode ov... | 03/25/2008 |
| 7339254 | SOI substrate for integration of opto-electronics with SiGe BiCMOS According to an exemplary embodiment, a structure includes a silicon-on-insulator substrate including a buried oxide layer situated over a bulk silicon substrate and a silicon layer situated over the buried oxide layer. The structure further includes a trench formed... | 03/04/2008 |
| 7329940 | Semiconductor structure and method of manufacture A structure comprises a single wafer with a first subcollector formed in a first region having a first thickness and a second subcollector formed in a second region having a second thickness, different from the first thickness. A method is also contemplated which in... | 02/12/2008 |
| 7319263 | Semiconductor component with switching element configured to reduce parasitic current flow A semiconductor component is described. In one embodiment, the semiconductor component includes a switching element integrated in the semiconductor component between two functional element semiconductor regions, configured to reduce a parasitic current flow through ... | 01/15/2008 |
| 7288827 | Self-aligned mask formed utilizing differential oxidation rates of materials A self-aligned oxide mask is formed utilizing differential oxidation rates of different materials. The self-aligned oxide mask is formed on a CVD grown base NPN base layer which compromises single crystal Si (or Si/SiGe) at active area and polycrystal Si (or Si/SiGe... | 10/30/2007 |
| 7247923 | Semiconductor device having a lateral MOSFET and combined IC using the same A semiconductor device realizes a high electrostatic discharge withstanding capability and a high surge withstanding capability within the narrow chip area of a lateral MOSFET used in integrated intelligent switching devices, double-integration-type signal input and... | 07/24/2007 |
| 7229886 | Method of forming an integrated circuit incorporating higher voltage devices and low voltage devices therein A method of forming an integrated circuit configured to accommodate higher voltage and low voltage devices. In one embodiment, the method of forming the integrated circuit includes forming a switch on a semiconductor substrate, and forming a driver switch of a drive... | 06/12/2007 |
| 7176548 | Complementary analog bipolar transistors with trench-constrained isolation diffusion A semiconductor substrate includes a pair of trenches filled with a dielectric material. Dopant introduced into the mesa between the trenches is limited from diffusing laterally when the substrate is subjected to thermal processing. Therefore, semiconductor devices ... | 02/13/2007 |
| 7087979 | Bipolar transistor with an ultra small self-aligned polysilicon emitter The intrinsic base region of a bipolar transistor is formed to avoid a chemical interaction between the chemicals used in a chemical mechanical polishing step and the materials used to form the base region. The method includes the step of forming a trench in a layer... | 08/08/2006 |
| 7081397 | Trench sidewall passivation for lateral RIE in a selective silicon-on-insulator process flow A lateral trench in a semiconductor substrate is formed by the following steps. Form a lateral implant mask (LIM) over a top surface of the semiconductor substrate. Implant a heavy dopant concentration into the substrate through the LIM to form a lateral implant reg... | 07/25/2006 |
| 7026690 | Memory devices and electronic systems comprising integrated bipolar and FET devices The invention includes BIFETRAM devices. Such devices comprise a bipolar transistor in combination with a field effect transistor (FET) in a three-dimensional stacked configuration. The memory devices can be incorporated within semiconductor-on-insulator (SOI) const... | 04/11/2006 |
| 6989557 | Bipolar junction transistor and fabricating method A bipolar junction transistor (BJT) includes a dielectric layer formed on a predetermined region of a substrate, an opening formed in the dielectric layer and a portion of the substrate being exposed, a heavily doped polysilicon layer formed on a sidewall of the ope... | 01/24/2006 |
| 6977425 | Semiconductor device having a lateral MOSFET and combined IC using the same A semiconductor device realizes a high electrostatic discharge withstanding capability and a high surge withstanding capability within the narrow chip area of a lateral MOSFET used in integrated intelligent switching devices, double-integration-type signal input and... | 12/20/2005 |
| 6972472 | Quasi self-aligned single polysilicon bipolar active device with intentional emitter window undercut An emitter stack for a quasi-self-aligned bipolar (NPN or PNP) transistor is formed where two layers over the emitter of a silicon substrate are windowed in a manner to under cut the top layer thereby exposing the substrate material. The emitter polysilicon structur... | 12/06/2005 |
| 6972466 | Bipolar transistors with low base resistance for CMOS integrated circuits Complementary metal-oxide-semiconductor (CMOS) integrated circuits with bipolar transistors and methods for fabrication are provided. A bipolar transistor may have a lightly-doped base region. To reduce the resistance associated with making electrical contact to the... | 12/06/2005 |
| 6967144 | Low doped base spacer for reduction of emitter-base capacitance in bipolar transistors with selectively grown epitaxial base A bipolar transistor structure includes a collector region having a first conductivity type formed in a semiconductor substrate. A base region is formed over the collector region; the base region includes a highly doped lower layer having a second conductivity type ... | 11/22/2005 |
| 6964907 | Method of etching a lateral trench under an extrinsic base and improved bipolar transistor In a BJT, the extrinsic base to collector capacitance is reduced by forming a lateral trench between the extrinsic base region and collector. This is typically done by using an anisotropic wet etch process in a direction of a orientation wafer. ... | 11/15/2005 |
| 6960820 | Bipolar transistor self-alignment with raised extrinsic base extension and methods of forming same A self-aligned bipolar transistor structure having a raised extrinsic base comprising an outer region and an inner region of different doping concentrations and methods of fabricating the transistor are disclosed. More specifically, the self-alignment of the extrins... | 11/01/2005 |
| 6943426 | Complementary analog bipolar transistors with trench-constrained isolation diffusion A semiconductor substrate includes a pair of trenches filled with a dielectric material. Dopant introduced into the mesa between the trenches is limited from diffusing laterally when the substrate is subjected to thermal processing. Therefore, semiconductor devices ... | 09/13/2005 |
| 6936509 | STI pull-down to control SiGe facet growth A SiGe bipolar transistor including a semiconductor substrate having a collector and sub-collector region formed therein, wherein the collector and sub-collector are formed between isolation regions that are also present in the substrate is provided. Each isolation ... | 08/30/2005 |
| 6911715 | Bipolar transistors and methods of manufacturing the same A bipolar transistor in which the occurrence of Kirk effect is suppressed when a high current is injected into the bipolar transistor and a method of fabricating the bipolar transistor are described. The bipolar transistor includes a first collector region of a firs... | 06/28/2005 |
| 6903417 | Power semiconductor device A semiconductor device including an N-type semiconductor substrate which includes arsenic as an impurity, a first electrode formed on a main surface of the N-type semiconductor substrate, a ground surface formed on another surface of the N-type semiconductor substra... | 06/07/2005 |
| 6903386 | Transistor with means for providing a non-silicon-based emitter A transistor includes a means for providing a non-silicon-based emitter with a flexible structure to relieve lattice mis-match between the emitter and the base. ... | 06/07/2005 |
| 6853017 | Bipolar transistor structure with ultra small polysilicon emitter A bipolar transistor structure includes trench isolation dielectric material formed in a semiconductor substrate to define a substrate active device region. A collector region is formed beneath the surface of the active device region. A base region is formed in the ... | 02/08/2005 |
| 6853048 | Bipolar transistor having an isolation structure located under the base, emitter and collector and a method of manufacture thereof The present invention provides a bipolar transistor and a method of manufacture thereof. The bipolar transistor includes a dielectric region located in a semiconductor substrate and a collector located in the semiconductor substrate and at least partially over the d... | 02/08/2005 |
| 6847094 | Contact structure on a deep region formed in a semiconductor substrate The forming of a contact with a deep region of a first conductivity type formed in a silicon substrate. The contact includes a doped silicon well region of the first conductivity type and an intermediary region connected between the deep layer and the well. This int... | 01/25/2005 |
| 6844594 | Minimally spaced gates and word lines A method of forming minimally spaced word lines is described. A double exposure technique is employed at the gate formation level. A small trench is defined through gate stack layers by using a tapered etch or spacers to achieve the desired width of the trench. A fi... | 01/18/2005 |
| 6838709 | Bipolar transistor A bipolar transistor includes the first group of transistors 610a, the second group of transistors 610b, the third group of transistors 610c and the fourth group of transistors 610d. The groups of transistors h... | 01/04/2005 |
| 6828649 | Semiconductor device having an interconnect that electrically connects a conductive material and a doped layer, and a method of manufacture therefor The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the same. In one advantageous embodiment, the semiconductor device includes a doped layer located over a semiconductor substrate, and an isol... | 12/07/2004 |
| 6828651 | Integrated structure An integrated structure formed on a semiconductor chip includes a substrate having a first conductivity type and an epitaxial layer grown on the substrate. The epitaxial layer may have the first conductivity type and also a conductivity less than a conductivity of t... | 12/07/2004 |
| 6806550 | Evaluation configuration for semiconductor memories An evaluation configuration has a first MOS evaluation stage, an isolation stage, and a bipolar evaluation stage. The isolation stage is connected between the first MOS evaluation stage and the bipolar evaluation stage. The isolation stage isolates the first MOS eva... | 10/19/2004 |
| 6798041 | Method and system for providing a power lateral PNP transistor using a buried power buss A power lateral PNP device is disclosed which includes an epitaxial layer; a first and second collector region embedded in the epitaxial layer, an emitter region between the first and second collector regions. Therefore slots are placed in each of the regions. Accor... | 09/28/2004 |
