Class 257/515 - With active junction abutting groove (e.g., "walled emitter")

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: Subject matter wherein at least one pn junction forming
No. of patents: 110
Last issue date: 04/15/2008

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Number	Title	Issue Date
7358108	CMOS image sensor and method for fabricating the same A CMOS image sensor and a method for fabricating the same are disclosed, in which the boundary between an active region and a field region is not damaged by ion implantation. The method for fabricating a CMOS image sensor includes forming a trench in a first conduct...	04/15/2008
7304390	Anisotropic conductive sheet and manufacture thereof An anisotropic conductive sheet manufactured through improved manufacturing steps and a method of manufacturing the same. Conductive portions are unevenly arranged in a nonconductive elastomer having fluidity and serving as a matrix, the conductive portions highly d...	12/04/2007
7279769	Semiconductor device and manufacturing method thereof To suppress occurrence of dislocation in a substrate of a semiconductor device at an end portion of a gate electrode. Provided is a semiconductor device having a plurality of element formation regions formed over the main surface of a semiconductor substrate, an ele...	10/09/2007
7105908	SRAM cell having stepped boundary regions and methods of fabrication A semiconductor device comprises a substrate. In addition, the semiconductor device comprises an active region and an isolation region. The active region is in the substrate and comprises a semiconductor material. The isolation region is also in the substrate, adjac...	09/12/2006
7101750	Semiconductor device for integrated injection logic cell and process for fabricating the same A semiconductor device for an integrated injection logic cell having a pnp bipolar transistor structure formed on a semiconductor substrate, wherein at least one layer of insulating films formed on a base region of the pnp bipolar transistor structure is comprised o...	09/05/2006
7038290	Integrated circuit device An integrated circuit device comprising: a body of a first solid material having an upper surface and a major bottom surface; a pocket of a second solid material having a top surface and a side surface, and a botto...	05/02/2006
7026695	Method and apparatus to reduce parasitic forces in electro-mechanical systems An electro-mechanical system, the system comprising a first surface with an electrically activated electrode coupled to the first surface and to an electrical source to receive a first signal. The system further comprising a moveable structure suspended at a first h...	04/11/2006
6919615	Semiconductor device for integrated injection logic cell and process for fabricating the same A semiconductor device for an integrated injection logic cell having a pnp bipolar transistor structure formed on a semiconductor substrate, wherein at least one layer of insulating films formed on a base region of the pnp bipolar transistor structure is comprised o...	07/19/2005
6882025	Strained-channel transistor and methods of manufacture A semiconductor device includes a region of semiconductor material with first and second isolation trenches formed therein. The first isolation trench is lined with a first material having a low oxygen diffusion rate and is filled with an insulating material. The se...	04/19/2005
6875649	Methods for manufacturing integrated circuit devices including an isolation region defining an active region area Integrated circuit devices including an isolation region are provided. The devices include an integrated circuit substrate and a trench in the integrated circuit substrate that defines an active region of the integrated circuit device. A silicon layer is provided on...	04/05/2005
6867472	Reduced hot carrier induced parasitic sidewall device activation in isolated buried channel devices by conductive buried channel depth optimization A semiconductor device includes a transistor junction formed in a substrate adjacent to an isolation region. A region between the transistor junction and the isolation region includes an area susceptible to hot carrier effects. The transistor junction extends from a...	03/15/2005
6847094	Contact structure on a deep region formed in a semiconductor substrate The forming of a contact with a deep region of a first conductivity type formed in a silicon substrate. The contact includes a doped silicon well region of the first conductivity type and an intermediary region connected between the deep layer and the well. This int...	01/25/2005
6703679	Low-resistivity microelectromechanical structures with co-fabricated integrated circuit A microfabricated device includes a substrate having a device layer and substantially filled, isolating trenches; a doped region of material formed by photolithographically defining a region for selective doping of said device layer, selectively doping sa...	03/09/2004
6696743	Semiconductor transistor having gate electrode and/or gate wiring A semiconductor transistor formed between trench device isolation regions comprises; a gate electrode formed on a device formation region with the intervention of a gate insulating film and extended over the trench device isolation regions, a distance fro...	02/24/2004
6693325	Semiconductor device having silicon on insulator and fabricating method therefor The present invention relates to a highly integrated SOI semiconductor device and a method for fabricating the SOI semiconductor device by reducing a distance between diodes or well resistors without any reduction in insulating characteristics. The device...	02/17/2004
6683364	Integrated circuit devices including an isolation region defining an active region area and methods for manufacturing the same Integrated circuit devices including an isolation region are provided. The devices include an integrated circuit substrate and a trench in the integrated circuit substrate that defines an active region of the integrated circuit device. A silicon layer is ...	01/27/2004
6661076	Semiconductor device A semiconductor device in which the potential of a conductive support substrate can be kept to be a predetermined potential, while an SOI substrate is used as a chip substrate, without adding a new step and providing a rear electrode, is provided. In a ch...	12/09/2003
6661077	Semiconductor device including primary connecting plug and an auxiliary connecting plug In order that the yield can be enhanced, the method of manufacturing a semiconductor device comprises the steps of: forming first holes 101a not penetrating a support side silicon wafer 101; forming a ground insulating film 102; forming primary connection...	12/09/2003
6646320	Method of forming contact to poly-filled trench isolation region Existing polysilicon emitter technology is used to contact poly fill in a trench isolation structure. A standard single poly emitter window process is followed. An "emitter window" is masked directly over the polysilicon trench fill. Heavily doped single ...	11/11/2003
6555891	SOI hybrid structure with selective epitaxial growth of silicon A method and structure for selectively growing epitaxial silicon in a trench formed within a silicon-on-insulator (SOI) structure. The SOI structure includes a buried oxide layer (BOX) on a bulk silicon substrate, and a silicon layer on the BOX. A pad lay...	04/29/2003
6545302	Image sensor capable of decreasing leakage current between diodes and method for fabricating the same An image sensor capable of preventing the degradation of pinned photodiodes and the generation of leakage current between neighboring pinned photodiodes is provided. The disclosed image sensor contains a plurality of pixel units, each pixel unit having a ...	04/08/2003
6525403	Semiconductor device having MIS field effect transistors or three-dimensional structure A semiconductor projection is formed on a semiconductor substrate of the first conductivity type and has a semiconductor layer of the first conductivity type. The semiconductor projection has a top surface and side surfaces. A gate electrode is formed abo...	02/25/2003
6448606	Semiconductor with increased gate coupling coefficient A reduced device geometry semiconductor memory device is provided which has increased device efficiency because of an increased gate coupling coefficient. Shallow trench isolations are formed in a semiconductor substrate. The shallow trench isolations are...	09/10/2002
6404020	Method of forming contact pads in a semiconductor device and a semiconductor device formed using the method A semiconductor device having a self-aligned contact pad and the method for manufacturing the device are disclosed. The semiconductor device includes: an isolation region formed in a semiconductor substrate; multiple conductive structures formed on the to...	06/11/2002
6380599	Method and apparatus for trench isolation process with pad gate and trench edge spacer elimination A microelectronic device includes a field oxide isolation pad which extends from a trench formed in a microelectronic substrate by a height which is less than approximately two times the height of a gate structure formed on the microelectronic substrate. ...	04/30/2002
6329699	Bipolar transistor with trenched-groove isolation regions The invention relates to semiconductor devices having a bipolar transistor to form an isolation area within a base electrode contact area to ensure stable contact of the base electrode. The bipolar transistor formed in the transistor area is in the form o...	12/11/2001
6294817	Source/drain-on insulator (S/DOI) field effect transistor using oxidized amorphous silicon and method of fabrication Source and drain regions of field effect transistors are fabricated with an electrically insulating layer formed thereunder so as to reduce junction capacitance between each and a semiconductor body in which the regions are formed. Shallow trench isolatio...	09/25/2001
6261920	N-channel MOSFET having STI structure and method for manufacturing the same A semiconductor device includes an n-channel MOSFET isolated by an element isolation region of STI structure. A silicon nitride (SiN) region is formed in an Si substrate near the interface between the element isolation region and the Si substrate. The sil...	07/17/2001
6222224	Erasable and programmable nonvolatile semiconductor memory, semiconductor integrated circuit device having the semiconductor memory and method of manufacturing the semiconductor memory A nonvolatile semiconductor memory has memory cells (1) each having an insulated-gate FET that has an information storage part. A semiconductor region (27) is formed at the surface of a channel region of each memory cell. The semiconductor region has the ...	04/24/2001
6144086	Structure for improved latch-up using dual depth STI with impurity implant A method and structure for improving the latch-up characteristic of semiconductor devices is provided. A dual depth STI is used to isolate the wells from each other. The trench has a first substantially horizontal surface at a first depth and a second sub...	11/07/2000
6127720	Semiconductor device and method for manufacturing the same A semiconductor device provided with a wide and shallow first groove and a second groove in the first groove area, having a narrower width than that of the first groove around a predetermined area in a one-conductive area provided in the upper region of a...	10/03/2000
6040617	Structure to provide junction breakdown stability for deep trench devices The present invention is directed to an improved deep trench structure, for use in junction devices, which addresses junction breakdown voltage instabilities of the prior art. The primary, or metallurgical, junction where avalanche breakdown occurs is mov...	03/21/2000
6020621	Stress-free shallow trench isolation A trench isolation in a semiconductor substrate is provided. The trench isolation includes a recessed region in the semiconductor substrate. The trench isolation also has a first insulator layer lining the recessed region. The first insulator aligns with ...	02/01/2000
5994756	Substrate having shallow trench isolation A semiconductor substrate having a shallow trench isolation (STI) structure and a method of manufacturing the same are provided, i.e., an isolation substrate in which grooves are selectively formed at predetermined locations of the semiconductor substrate...	11/30/1999
5990536	Integrated circuit arrangement having at least two mutually insulated components, and method for its production An integrated circuit arrangement having at least two components has in a substrate, an insulation structure (4', 5) between the components which covers at least one side of a trench (3) and is thicker at the bottom of the trench than at the neck of the t...	11/23/1999
5982017	Recessed structure for shallow trench isolation and salicide processes A shallow trench isolated FET LDD structure that has a low probability of short circuiting at the silicon to trench interface or between the source or drain and the gate (because of a titanium silicide bridge) is described. It is based on an isolation tre...	11/09/1999
5877539	Bipolar transistor with a reduced collector series resistance A collector structure in a bipolar transistor on a semiconductor substrate is surrounded by trench isolations. A well region has a first impurity concentration and extends in an upper portion of the semiconductor substrate surrounded by the trench isolati...	03/02/1999
5854509	Method of fabricating semiconductor device and semiconductor device Ordinary anisotropic etching is performed up to a depth (d1) while anisotropic etching is performed to form an inward taper from the depth (d1) by changing etching conditions such as components in a vapor phase and the temperature of a silicon substrate (...	12/29/1998
5635753	Integrated circuit Disclosed is an integrated circuit having at least two active components, such as transistors, having the following features: a highly conductive substrate is provided which is connected to one pole of a voltage supply source, a semiconductor layer, which is e...	06/03/1997
5583348	Method for making a schottky diode that is compatible with high performance transistor structures A method for making a schottky diode structure (10) simultaneously with a polysilicon contact structure (31,33) to a transistor is provided. In a single process step, a polysilicon layer is patterned to expose a single crystal semiconductor region (22a) o...	12/10/1996

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Class 257/515 - With active junction abutting groove (e.g., "walled emitter")