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Vladimir Zworykin, television pioneer ; Talking about an invention in which he played a critical role.
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| Number | Title | Issue Date |
| 8169048 | Isolation structure in a memory device An isolation structure in a memory device and a method for fabricating the isolation structure. In the method, a first trench is formed in a cell region of a semiconductor substrate and a second trench in a peripheral region of the semiconductor substrate. A liner l... | 05/01/2012 |
| 8026572 | Semiconductor device and method for manufacturing same A semiconductor device having plural active and passive elements on one semiconductor substrate is manufactured in the following cost effective manner even when the active and passive elements include double sided electrode elements. When the semiconductor substrate... | 09/27/2011 |
| 7880264 | Integrated circuit arrangement comprising isolating trenches and a field effect transistor A memory circuit arrangement and a fabrication method are disclosed. The memory circuit arrangement has a memory cell area. The memory cell area contains memory cell transistors, one column of which are selected using a triple gate area selection transistor. The tra... | 02/01/2011 |
| 7868414 | Isolated bipolar transistor A bipolar transistor is formed in an isolation structure comprising a floor isolation region, a dielectric filled trench above the floor isolation region and a sidewall isolation region extending downward from the bottom of the trench to the floor isolation region. ... | 01/11/2011 |
| 7834416 | Trench-constrained isolation diffusion for integrated circuit die A semiconductor substrate includes a pair of trenches filled with a dielectric material. Dopant introduced into the mesa between the trenches is limited from diffusing laterally when the substrate is subjected to thermal processing. Therefore, semiconductor devices ... | 11/16/2010 |
| 7829972 | Edge termination structure for semiconductor components A semiconductor component has a drift path (4) in a semiconductor body (5) of a semiconductor chip (6). The semiconductor component has an edge area (7) and a cell area (8), which is surrounded by the edge area (7). A trench... | 11/09/2010 |
| 7800198 | Isolation structures for integrated circuits A variety of isolation structures for semiconductor substrates include a trench formed in the substrate that is filled with a dielectric material or filled with a conductive material and lined with a dielectric layer along the walls of the trench. The trench may be ... | 09/21/2010 |
| 7573116 | Etch aided by electrically shorting upper and lower sidewall portions during the formation of a semiconductor device A method used to fabricate a semiconductor device comprises etching a dielectric layer, resulting in an undesirable charge buildup along a sidewall formed in the dielectric layer during the etch. The charge buildup along a top and a bottom of the sidewall may reduce... | 08/11/2009 |
| 7425751 | Method to reduce junction leakage current in strained silicon on silicon-germanium devices A MOSFET device in strained silicon-on-SiGe and a method of forming the device are described. The said device achieves reduced junction leakage due to the lower band-gap values of SiGe. The method consists of forming isolation trenches in a composite strained-Si/SiG... | 09/16/2008 |
| 7420262 | Electronic component and semiconductor wafer, and method for producing the same The invention relates to an electronic component and a semiconductor wafer, and a method for producing them. The semiconductor wafer has strip-type separating regions. The separating regions are provided with through contacts in the direction of the rear side of the... | 09/02/2008 |
| 7382015 | Semiconductor device including an element isolation portion having a recess A non-volatile semiconductor memory device, which is intended to prevent data destruction by movements of electric charges between floating gates and thereby improve the reliability, includes element isolation/insulation films buried into a silicon substrate to isol... | 06/03/2008 |
| 7358587 | Semiconductor structures In one aspect, the invention includes a method of forming a material within an opening, comprising: a) forming an etch-stop layer over a substrate, the etch-stop layer having an opening extending therethrough to expose a portion of the underlying substrate and compr... | 04/15/2008 |
| 7348254 | Method of fabricating fin field-effect transistors A method of fabricating a fin field-effect transistor that may enable a reduction in the number of process steps, by forming the fin structure by etching away a predetermined thickness of an element isolation layer. The method includes steps of sequentially forming ... | 03/25/2008 |
| 7345352 | Insulating tube, semiconductor device employing the tube, and method of manufacturing the same An insulating tube includes a underlying insulating film, a first sidewall insulating film disposed on the underlying insulating film, a second sidewall insulating film disposed on the underlying insulating film, opposite to the first sidewall insulating film so as ... | 03/18/2008 |
| 7332407 | Method and apparatus for a semiconductor device with a high-k gate dielectric A process and apparatus for a high-k gate dielectric MOS transistor is described. A substrate is provided, a high-k gate dielectric material is deposited over the substrate, a gate electrode layer is deposited over the dielectric material and a patterning step is pe... | 02/19/2008 |
| 7332790 | Semiconductor device having an active area partially isolated by a lateral cavity A process of making a partial silicon-on-insulator ledge is disclosed. A deep implantation region is created in a substrate. During a lateral cavity etch, the deep implantation region resists etching. The lateral cavity etch acts to partially isolate an active area ... | 02/19/2008 |
| 7329938 | Semiconductor integrated circuit A semiconductor integrated circuit includes a first cell spanning one of the p-wells and one of the n-wells adjacent to each other, and having one end on a dividing line inside the p-well and another end on a dividing line inside the n-well, and having a height dete... | 02/12/2008 |
| 7326983 | Selective silicon-on-insulator isolation structure and method A first aspect of the present invention is a method of forming an isolation structure including: (a) providing a semiconductor substrate; (b) forming a buried N-doped region in the substrate; (c) forming a vertical trench in the substrate, the trench extending into ... | 02/05/2008 |
| 7321139 | Transistor layout for standard cell with optimized mechanical stress effect A layout for a transistor in a standard cell is disclosed. The layout for a transistor includes an active region with at least one portion having a first edge and at least one portion having a second edge all perpendicular to a channel of the transistor; and a gate ... | 01/22/2008 |
| 7291541 | System and method for providing improved trench isolation of semiconductor devices A system and method is disclosed for providing improved trench isolation of semiconductor devices. An isolation trench of the present invention is manufactured as follows. A substrate of a semiconductor device is provided and a trench is etched in the substrate. The... | 11/06/2007 |
| 7288462 | Buffer zone for the prevention of metal migration Particle migration, such as silver electro-migration, on a flat ceramic surface is effectively eliminated by an upward vertical barrier formed on the surface or a groove formed in the surface between two silver conductors. ... | 10/30/2007 |
| 7279769 | Semiconductor device and manufacturing method thereof To suppress occurrence of dislocation in a substrate of a semiconductor device at an end portion of a gate electrode. Provided is a semiconductor device having a plurality of element formation regions formed over the main surface of a semiconductor substrate, an ele... | 10/09/2007 |
| 7279770 | Isolation techniques for reducing dark current in CMOS image sensors A structure for isolating areas in a semiconductor device is provided. The structure includes a trench having first and second portions formed in a substrate. The first portion has a first width, and the second portion has a second width and is below the first porti... | 10/09/2007 |
| 7276774 | Trench isolation structures for integrated circuits A dielectric film is formed by atomic layer deposition to conformally fill a narrow, deep trench for device isolation. The method of the illustrated embodiments includes alternately pulsing vapor-phase reactants in a string of cycles, where each cycle deposits no mo... | 10/02/2007 |
| 7274073 | Integrated circuit with bulk and SOI devices connected with an epitaxial region An integrated circuit having devices fabricated in both SOI regions and bulk regions, wherein the regions are connected by a trench filled with epitaxially deposited material. The filled trench provides a continuous semiconductor surface joining the SOI and bulk reg... | 09/25/2007 |
| 7268402 | Memory cell with trench-isolated transistor including first and second isolation trenches An isolation trench in a semiconductor includes a first isolation trench portion having a first depth and having a first sidewall intersecting a surface of the semiconductor at a first angle. A second isolation trench portion extends within and below the first isola... | 09/11/2007 |
| 7262477 | Semiconductor device There is provided a semiconductor device including a semiconductor substrate with a trench, and a particulate insulating layer filling at least a lower portion of the trench and containing insulating particles. The semiconductor device may further include a reflowab... | 08/28/2007 |
| 7259442 | Selectively doped trench device isolation A selectively doped trench isolation device is provided. The trench isolation device of the preferred embodiment includes a semiconductor substrate having a trench. A thin field oxide layer is grown on the side walls of the trench, and the trench is filled with a he... | 08/21/2007 |
| 7253047 | Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry are described. In one embodiment, active areas are formed over a substrate, with one of the ... | 08/07/2007 |
| 7239003 | Isolation techniques for reducing dark current in CMOS image sensors Isolation methods and devices for isolating regions of a semiconductor device. The isolation method and structure include forming an isolating trench in an active area and filling the trench with a doped conductive material containing silicon. Suitable conductive ma... | 07/03/2007 |
| 7235856 | Trench isolation for semiconductor devices In etching trench isolation structures, a pad oxide or sacrificial oxide may be formed with substantially the same (or higher) etch rate as the trench filler. Because the etch rate in the trench area is substantially similar to (or less than) the etch rate in the no... | 06/26/2007 |
| 7227237 | Systems and methods for biasing high fill-factor sensor arrays and the like A high fill-factor photosensor array is formed comprising a P-layer, an I-layer, one or more semiconductor structures adjacent to the I-layer and each coupled to a N-layer, an electrically conductive electrode formed on top of the P-layer, and an additional semicond... | 06/05/2007 |
| 7224038 | Semiconductor device having element isolation trench and method of fabricating the same A semiconductor device capable of preventing defective embedding of an insulator and improving the withstand voltage (dielectric strength) of an element isolation region is obtained. This semiconductor device comprises a semiconductor substrate having a main surface... | 05/29/2007 |
| 7221030 | Semiconductor device A pad oxide film and a silicon nitride film are formed on a semiconductor substrate. Next, after the patterning of the silicon nitride film, by etching the pad oxide film and the substrate, a first trench is formed in a first region and a second trench is formed in ... | 05/22/2007 |
| 7205617 | Semiconductor device including active regions and gate electrodes for field effect transistors, with a trench formed between the active regions A semiconductor device has p-channel field effect transistors disposed in a lattice shape. In order to generate compression stress in the channel of a p-channel field effect transistor, a long active region of a plurality of transistors is divided for each gate elec... | 04/17/2007 |
| 7196394 | Method and apparatus for a deposited fill layer A method of forming a semiconducting wafer is provided that utilizes fewer processing operations, reduces process variation, and lowers cost as well as production time. The method provided further improves via reliability by permitting vias to be formed with consist... | 03/27/2007 |
| 7176549 | Shallow trench isolation using low dielectric constant insulator A shallow trench isolation is disclosed wherein the trench depth is reduced beyond that achieved in prior art processes. The reduced trench depth helps to eliminate the formation of voids during the trench refill process and provides for greater planarity in the fin... | 02/13/2007 |
| 7176105 | Dielectric gap fill with oxide selectively deposited over silicon liner A thin layer of silicon is deposited within a high aspect ratio feature to provide a template for selective deposition of oxide therein. In accordance with one embodiment, amorphous silicon is deposited within a shallow trench feature overlying an oxide liner grown ... | 02/13/2007 |
| 7170109 | Heterojunction semiconductor device with element isolation structure A technique enabling to improve element isolation characteristic of a semiconductor device is provided. An element isolation structure is provided in a semiconductor substrate in which a silicon layer, a compound semiconductor layer and a semiconductor layer are lam... | 01/30/2007 |
| 7157770 | MOS transistor with recessed gate and method of fabricating the same A MOS transistor with a recessed gate and a method of fabricating the same: The MOS transistor comprises a semiconductor substrate, and a trench isolation layer located in a predetermined region of the semiconductor substrate for defining an active region. The trenc... | 01/02/2007 |
