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| Number | Title | Issue Date |
| 7342293 | Bipolar junction transistors (BJTS) with second shallow trench isolation (STI) regions, and methods for forming same The present invention relates to bipolar junction transistors (BJTS). The collector region of each BJT is located in a semiconductor substrate surface and adjacent to a first shallow trench isolation (STI) region. A second STI region is provided, which extends betwe... | 03/11/2008 |
| 7329938 | Semiconductor integrated circuit A semiconductor integrated circuit includes a first cell spanning one of the p-wells and one of the n-wells adjacent to each other, and having one end on a dividing line inside the p-well and another end on a dividing line inside the n-well, and having a height dete... | 02/12/2008 |
| 7304390 | Anisotropic conductive sheet and manufacture thereof An anisotropic conductive sheet manufactured through improved manufacturing steps and a method of manufacturing the same. Conductive portions are unevenly arranged in a nonconductive elastomer having fluidity and serving as a matrix, the conductive portions highly d... | 12/04/2007 |
| 7235857 | Power semiconductor device A semiconductor device is provided in which a plurality of MOSFETs including a vertical MOSFET is formed on a substrate. The device includes a silicon carbide substrate having front and back surfaces facing each other, an isolating region formed in the substrate to ... | 06/26/2007 |
| 7161382 | General-purpose logic cell, general-purpose logic cell array using the same, and ASIC using general-purpose logic cell array A general-purpose logic cell used in a general-purpose logic cell array for a logic circuit, includes a plurality of kinds of logic circuit elements, each of which has a plurality of terminals with no connection. The plurality of kinds of logic circuit elements incl... | 01/09/2007 |
| 7129562 | Dual-height cell with variable width power rail architecture A standard cell architecture with a basic cell that spans multiple rows of the standard cell. This multi-row basic cell may be a dual-height cell that spans two rows, or it may span more than two rows. The multi-row basic cell may be intermixed in a standard cell de... | 10/31/2006 |
| 7071527 | Semiconductor element and manufacturing method thereof A p-channel MOSFET (1) includes a semiconductor substrate (2), an epitaxial region (3), a second diffusion region (6), and a drain region. The epitaxial region (3) is formed on the upper surface of the semiconductor substrate (2... | 07/04/2006 |
| 7067899 | Semiconductor integrated circuit device A semiconductor integrated circuit device according to the invention includes an N-type embedded diffusion region between a substrate and a first epitaxial layer in island regions serving as small signal section. The substrate and the first epitaxial layer are thus ... | 06/27/2006 |
| 6960818 | Recessed shallow trench isolation structure nitride liner and method for making same A method for reducing hot carrier reliability problems within an integrated circuit device. The method includes forming a shallow trench isolation structure incorporated with the device by filling a trench with a photoresist plug and removing a portion of the photor... | 11/01/2005 |
| 6949391 | Method of fabricating bottom-gated polycrystalline silicon thin film transistor A method of forming a thin film transistor includes forming a gate electrode on a substrate, forming a gate insulating layer on the gate electrode, forming an amorphous silicon layer on the gate insulating layer, crystallizing the amorphous silicon layer within an a... | 09/27/2005 |
| 6838713 | Dual-height cell with variable width power rail architecture A standard cell architecture with a basic cell that spans multiple rows of the standard cell. This multi-row basic cell may be a dual-height cell that spans two rows, or it may span more than two rows. The multi-row basic cell may be intermixed in a standard cell de... | 01/04/2005 |
| 6828649 | Semiconductor device having an interconnect that electrically connects a conductive material and a doped layer, and a method of manufacture therefor The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the same. In one advantageous embodiment, the semiconductor device includes a doped layer located over a semiconductor substrate, and an isol... | 12/07/2004 |
| 6803622 | Semiconductor device and method of manufacturing the same A semiconductor device includes a semiconductor substrate; a first insulating film formed on the top surface of the semiconductor substrate; a first gate electrode formed on the first insulating film; a second insulating film having a three-layered structure made by... | 10/12/2004 |
| 6750527 | Semiconductor integrated circuit device having a plurality of wells, test method of testing the semiconductor integrated circuit device, and test device which executes the test method A semiconductor device comprises a semiconductor substrate of a first conductivity type, at least one first well of a second conductivity type formed in the semiconductor substrate, and at least one second well of the first conductivity type formed in at least one f... | 06/15/2004 |
| 6700158 | Trench corner protection for trench MOSFET A method of making a trench MOSFET structure having upper trench corner protection, the method not requiring trench corner rounding or sacrificial oxide/strip steps. The trench MOSFET structure fabricated according to the method of the present invention e... | 03/02/2004 |
| 6674148 | Lateral components in power semiconductor devices A method for adjusting the gain or the sensitivity of a lateral component formed in the front surface of a semiconductor wafer, having a first conductivity type, includes not doping or overdoping, according to the first conductivity type, the back surface... | 01/06/2004 |
| 6624497 | Semiconductor device with a reduced mask count buried layer An N type buried layer is formed, in one embodiment, by a non selective implant on the surface of a wafer and later diffusion. Subsequently, the wafer is masked and a selective P type buried layer is formed by implant and diffusion. The coefficient of dif... | 09/23/2003 |
| 6525403 | Semiconductor device having MIS field effect transistors or three-dimensional structure A semiconductor projection is formed on a semiconductor substrate of the first conductivity type and has a semiconductor layer of the first conductivity type. The semiconductor projection has a top surface and side surfaces. A gate electrode is formed abo... | 02/25/2003 |
| 6469362 | High-gain pnp bipolar junction transistor in a CMOS device and method for forming the same An integrated circuit device includes a semiconductor substrate, an NMOS, a PMOS contiguous with the NMOS, and a composite pnp bipolar junction transistor contiguous with the NMOS. The composite pnp bipolar junction transistor includes a lateral npn bipol... | 10/22/2002 |
| 6441444 | Semiconductor device having a nitride barrier for preventing formation of structural defects Providing a method of producing a semiconductor device and a structure of the semiconductor device employing a trench isolation structure for isolating semiconductor elements wherein volumetric expansion of a trench-filling material due to oxidation proce... | 08/27/2002 |
| 6365957 | Lateral bipolar transistor An object of the present invention is to provide a lateral bipolar transistor having a high current driving capacity and a high current amplification factor as well as a high cut-off frequency. A device area 13 surrounded by an isolating insulation layer is fo... | 04/02/2002 |
| 6285073 | Contact structure and method of formation The horizontal surface area required to contact semiconductor devices, in integrated circuits fabricated with trench isolation, is minimized without degrading contact resistance by utilizing the vertical surface area of the trench sidewall. A trench isola... | 09/04/2001 |
| 6127718 | Semiconductor device and method of manufacturing the same The semiconductor device and method of manufacturing the same according to the present invention has an object of reducing hem-pulling at a side wall of an isolation trench caused at an open space of a device isolation region having a well boundary at its... | 10/03/2000 |
| 6060346 | Semiconductor device and method for manufacturing the same A semiconductor device and a method for manufacturing the same that forms a self-aligned contact hole between two gate lines. A substrate is provided that has a first gate line formed thereon. An insulator is formed on the first gate line and substrate. T... | 05/09/2000 |
| 6049131 | Device formed by selective deposition of refractory metal of less than 300 Angstroms of thickness A method and the device produced by the method of selective refractory metal growth/deposition on exposed silicon, but not on the field oxide is disclosed. The method includes preconditioning a wafer in a DHF dip followed by the steps of 1) selectively de... | 04/11/2000 |
| 5949125 | Semiconductor device having field isolation with a mesa or mesas Narrow and wide, planar field isolation region (72, 74, 152, 172, 182) is formed by forming trenches (52, 54) within a substrate (10). For wide, planar field isolation regions (72, 152, 172, 182), the trenches (52) define at least one mesa (76, 150, 170, ... | 09/07/1999 |
| 5945726 | Lateral bipolar transistor A substantially concentric lateral bipolar transistor having a base region that is disposed about a periphery of an emitter region, and a collector region that is disposed about a periphery of the base region to form the concentric lateral bipolar transis... | 08/31/1999 |
| 5915186 | Method of manufacturing heterojunction bipolar device having Si1-x Gex base In a semiconductor device manufacturing method for forming first and second bipolar transistors on a semiconductor substrate 1, a link base layer 5 for connecting a graft base layer (graft base layer 8) of the first bipolar transistor and an intrinsic bas... | 06/22/1999 |
| 5521399 | Advanced silicon on oxide semiconductor device structure for BiCMOS integrated circuit A bonded, SOI wafer which has stepped isolation trenches and sublayer interconnections first formed in a bulk silicon wafer. After these process steps are complete, a thin polysilicon layer is formed on the planarized upper surface of the bulk silicon waf... | 05/28/1996 |
| 5481130 | Semiconductor IIL device with dielectric and diffusion isolation n type epitaxial layers are formed on the main surface of a p type semiconductor substrate. A field oxide film is selectively formed in the surface of n type epitaxial layers. An n type diffusion region is formed in n type epitaxial layers positioned dire... | 01/02/1996 |
| 5376822 | Heterojunction type of compound semiconductor integrated circuit A heterojunction type of compound semiconductor integrated circuit in which a PNP transistor has an N type substrate made of a first compound semiconductor for mounting the PNP transistor and for insulating positive holes transmitted in the PNP transistor... | 12/27/1994 |
| 4947230 | Base-coupled transistor logic A base-coupled logic gate is characterized by input Schottky diodes that are directly formed on the base region of the switching transistor for the gate. A logic of this type provides flexible circuit arrangements and savings in a required area, while ach... | 08/07/1990 |
| 4935800 | Semiconductor integrated circuit This invention discloses a semiconductor integrated circuit in which an analog circuit and a digital circuit are formed on a single chip. The semiconductor integrated circuit includes a p-type semiconductor region, an n+ -type buried region for... | 06/19/1990 |
| 4933737 | Polysilon contacts to IC mesas A bipolar transistor comprises an n-type Si semiconductor body having a convex portion, an insulation film covering the surface of the semiconductor body other than the convex portion, and a p-type polycrystalline Si layer formed on the insulation film. A... | 06/12/1990 |
| 4819055 | Semiconductor device having a PN junction formed on an insulator film The invention deals with a semiconductor device which comprises a semiconductor substrate of a first conductivity type, a semiconductor region formed on said substrate, and a first insulation film provided between said semiconductor region and said semico... | 04/04/1989 |
| 4814846 | Photoelectric converting device A photoelectric converting device is provided with photoelectric converting cells. Each cell is provided with a semiconductor transistor and a capacitor. The transistor is composed of two main electrode semiconductor areas of a first type and a control el... | 03/21/1989 |
| 4813017 | Semiconductor memory device and array A memory array fabricated on a silicon substrate consists of memory cells each having two lateral p-n-p load-injector transistors and two vertical n-p-n flip-flop transistors with the p-n-p's being formed in a portion of the substrate which is electricall... | 03/14/1989 |
| 4789884 | IIL circuit with PNP injector A multi-stage IIL circuit is provided which includes common IIL elements each using a PNP transistor as an injector and an NPN transistor as an inverter, and inverse IIL elements each using an NPN transistor as an injector and a PNP transistor as an inver... | 12/06/1988 |
| 4729964 | Method of forming twin doped regions of the same depth by high energy implant First conductivity type impurity ions are implanted at a predetermined depth all over a region where impurity ions are to be implanted, and second conductivity type impurity ions are implanted in a dose about twice as large as that of the first conductivi... | 03/08/1988 |
| 4656495 | Bipolar ram cell and process An integrated bipolar RAM cell and process for its manufacture is disclosed. The RAM cell includes first and second cross-coupled bipolar transistors with first and second load elements coupled to the collectors of the first and second transistors, respec... | 04/07/1987 |
