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| Number | Title | Issue Date |
| 8044488 | Semiconductor device having particular impurity density characteristics The invention is based upon a semiconductor device where a high voltage bipolar transistor is manufactured on the same wafer with a high-speed bipolar transistor, and has a characteristic that the high-speed bipolar transistor and the high voltage bipolar transistor... | 10/25/2011 |
| 7923810 | Semiconductor devices having active elements with raised semiconductor patterns and related methods of fabricating the same A semiconductor device may include a semiconductor region of a semiconductor substrate wherein a P-N junction is defined between the semiconductor region and a bulk of the semiconductor substrate. An insulating isolation structure in the semiconductor substrate may ... | 04/12/2011 |
| 7911023 | Semiconductor apparatus including a double-sided electrode element and method for manufacturing the same A semiconductor apparatus is disclosed. The semiconductor apparatus includes a semiconductor substrate that has a first surface and a second surface opposite to each other. The semiconductor apparatus further includes multiple double-sided electrode elements each ha... | 03/22/2011 |
| RE41477 | Semiconductor device with a reduced mask count buried layer An N type buried layer is formed, in one embodiment, by a non selective implant on the surface of a wafer and later diffusion. Subsequently, the wafer is masked and a selective P type buried layer is formed by implant and diffusion. The coefficient of diffusion of t... | 08/10/2010 |
| 7755161 | Semiconductor devices A device comprises a first sub-collector formed in an upper portion of a substrate and a lower portion of a first epitaxial layer and a second sub-collector formed in an upper portion of the first epitaxial layer and a lower portion of a second epitaxial layer. The ... | 07/13/2010 |
| 7719081 | Semiconductor device and method of manufacturing the same In a semiconductor device of the present invention, an epitaxial layer is formed on a P type single crystal silicon substrate. Isolation regions are formed in the epitaxial layer, and are divided into a plurality of element formation regions. An NPN transistor is fo... | 05/18/2010 |
| 7582949 | Semiconductor devices A design structure embodied in a machine readable medium used in a design process. The design structure includes a first sub-collector formed in an upper portion of a substrate and a lower portion of a first epitaxial layer, and a second sub-collector formed in an u... | 09/01/2009 |
| 7582948 | Integrated transistor, particularly for voltages and method for the production thereof Integrated transistor and method for the production is disclosed. An explanation is given of, inter alia, a transistor having an electrically insulating isolating trench extending from a main area in the direction of a connection region remote from the main area. Mo... | 09/01/2009 |
| 7538409 | Semiconductor devices A device comprises a first sub-collector formed in an upper portion of a substrate and a lower portion of a first epitaxial layer and a second sub-collector formed in an upper portion of the first epitaxial layer and a lower portion of a second epitaxial layer. The ... | 05/26/2009 |
| 7400024 | Formation of deep trench airgaps and related applications A method for forming deep trench or via airgaps in a semiconductor substrate is disclosed comprising the steps of patterning a hole in the substrate, partly fill said hole with a sacrificial material (e.g. poly-Si), depositing spacers on the sidewalls of the unfille... | 07/15/2008 |
| 7372109 | Diode and applications thereof A diode with low substrate current leakage and suitable for BiCMOS process technology. A buried layer is formed on a semiconductor substrate. A connection region and well contact the buried layer. Isolation regions are adjacent to two sides of the buried layer, each... | 05/13/2008 |
| 7342293 | Bipolar junction transistors (BJTS) with second shallow trench isolation (STI) regions, and methods for forming same The present invention relates to bipolar junction transistors (BJTS). The collector region of each BJT is located in a semiconductor substrate surface and adjacent to a first shallow trench isolation (STI) region. A second STI region is provided, which extends betwe... | 03/11/2008 |
| 7332778 | Semiconductor device and method of manufacturing same To refine a semiconductor device (100), in particular a S[ilicon]O[n]I[nsulator] device, comprising: at least one isolating layer (10) made of a dielectric material; at least one silicon substrate ( | 02/19/2008 |
| 7309905 | Bipolar-based SCR for electrostatic discharge protection A system and method is disclosed for implementing a new bipolar-based silicon controlled rectifier (SCR) circuit for an electrostatic discharge (ESD) protection. The SCR circuit comprises a bipolar device to be formed on a semiconductor substrate. The bipolar device... | 12/18/2007 |
| 7276784 | Semiconductor device and a method of assembling a semiconductor device A semiconductor device includes a base substrate; a first fixing layer provided on the base substrate; a first semiconductor chip fixed on the first fixing layer; a first substrate provided above the first semiconductor chip; a plurality of first connection members ... | 10/02/2007 |
| 7271414 | Semiconductor device and method for fabricating the same A semiconductor device includes a transistor of a first conductivity type and a transistor of a second conductivity type. The transistor of the first conductivity type includes a first gate portion formed on a first region of a semiconductor substrate, a first sidew... | 09/18/2007 |
| 7242071 | Semiconductor structure A structure comprises a deep sub-collector buried in a first epitaxial layer and a near sub-collector buried in a second epitaxial layer. The structure further comprises a deep trench isolation structure isolating a region which is substantially above the deep sub-c... | 07/10/2007 |
| 7235856 | Trench isolation for semiconductor devices In etching trench isolation structures, a pad oxide or sacrificial oxide may be formed with substantially the same (or higher) etch rate as the trench filler. Because the etch rate in the trench area is substantially similar to (or less than) the etch rate in the no... | 06/26/2007 |
| 7232713 | Methods of forming interconnect lines In one aspect, the invention provides a method of forming an electrical connection in an integrated circuitry device. According to one preferred implementation, a diffusion region is formed in semiconductive material. A conductive line is formed which is laterally s... | 06/19/2007 |
| 7190042 | Self-aligned STI for narrow trenches A self-aligned shallow trench isolation region for a memory cell array is formed by etching a plurality of vertical deep trenches in a substrate and coating the trenches with an oxidation barrier layer. The oxidation barrier layer is recessed in portions of the tren... | 03/13/2007 |
| 7173320 | High performance lateral bipolar transistor A lateral bipolar transistor includes an emitter region, a base region, a collector region, and a gate disposed over the base region. A bias line is connected to the gate for applying a bias voltage thereto during operation of the transistor. The polarity of the bia... | 02/06/2007 |
| 7157360 | Memory device and method for forming a passivation layer thereon A memory device with an improved passivation structure. The memory device includes a semiconductor substrate with memory units thereon, an interconnect structure over the surface of the semiconductor substrate to connect with the memory units, and a passivation stru... | 01/02/2007 |
| 7157751 | Display device The present invention realizes a display device having C-MOS p-Si TFTs which enable the high integration by reducing spaces for P-MOS TFTs and N-MOS TFTs in driving circuit or the like thereof. The present invention adopts a self-aligned C-MOS process which uses a h... | 01/02/2007 |
| 7105908 | SRAM cell having stepped boundary regions and methods of fabrication A semiconductor device comprises a substrate. In addition, the semiconductor device comprises an active region and an isolation region. The active region is in the substrate and comprises a semiconductor material. The isolation region is also in the substrate, adjac... | 09/12/2006 |
| 7103864 | Semiconductor device, and design method, inspection method, and design program therefor A design method for automatically determining layout of a multilayer semiconductor device which has circuit blocks formed on a semiconductor substrate and measurement terminals for measuring voltage, logic state, or the like, on wiring lines for connecting the circu... | 09/05/2006 |
| 7067899 | Semiconductor integrated circuit device A semiconductor integrated circuit device according to the invention includes an N-type embedded diffusion region between a substrate and a first epitaxial layer in island regions serving as small signal section. The substrate and the first epitaxial layer are thus ... | 06/27/2006 |
| 7064416 | Semiconductor device and method having multiple subcollectors formed on a common wafer A semiconductor device and a method of fabricating a semiconductor device having multiple subcollectors which are formed in a common wafer, in order to provide multiple structures having different characteristic and frequency response are provided. The subcollectors... | 06/20/2006 |
| 7037818 | Apparatus and method for staircase raised source/drain structure A structure, apparatus and method for improving the performance of semiconductor devices is provided. The semiconductor structure includes a raised source/drain region above a planar source/drain. The raised source/drain has at least a first step and a second step w... | 05/02/2006 |
| 7027316 | Access circuit and method for allowing external test voltage to be applied to isolated wells An access circuit selectively couples an externally accessible terminal to each of a plurality of isolated DRAM wells in which respective DRAM arrays are fabricated. The access circuit for each well includes first and second transistors fabricated in respective well... | 04/11/2006 |
| 7002232 | Semiconductor integrated circuit device and method of testing the same A semiconductor integrated circuit device includes a semiconductor substrate of a first conductive type, a first well of a second conductive type provided in the semiconductor substrate, a second well of the first conductive type provided in the first well, a third ... | 02/21/2006 |
| 6979624 | Reduced mask count buried layer process An N type buried layer is formed, in one embodiment, by a non selective implant on the surface of a wafer and later diffusion. Subsequently, the wafer is masked and a selective P type buried layer is formed by implant and diffusion. The coefficient of diffusion of t... | 12/27/2005 |
| 6972471 | Deep trench isolation structure of a high-voltage device and method for forming thereof A deep trench isolation structure of a high-voltage device and a method of forming thereof. An epitaxial layer with a second type conductivity is formed on a semiconductor silicon substrate with a first type conductivity. A deep trench passes through the epitaxial l... | 12/06/2005 |
| 6960818 | Recessed shallow trench isolation structure nitride liner and method for making same A method for reducing hot carrier reliability problems within an integrated circuit device. The method includes forming a shallow trench isolation structure incorporated with the device by filling a trench with a photoresist plug and removing a portion of the photor... | 11/01/2005 |
| 6927116 | Semiconductor device having a double-well structure and method for manufacturing the same A first well of the same conductivity type as that of a semiconductor substrate and a second well of a conductivity type opposite to that of the semiconductor substrate, are formed in the semiconductor substrate. The second well isolates the semiconductor substrate ... | 08/09/2005 |
| 6924543 | Method for making a semiconductor device having increased carrier mobility A method and apparatus for a semiconductor device having increased electrical carrier mobility is described. That method and apparatus comprises forming two recesses within a substrate, and providing a material within the two recesses. The material has a predetermin... | 08/02/2005 |
| 6909164 | High performance vertical PNP transistor and method The invention includes a method and resulting structure for fabricating high performance vertical NPN and PNP transistors for use in BiCMOS devices. The resulting high performance vertical PNP transistor includes an emitter region including silicon and germanium, an... | 06/21/2005 |
| 6903386 | Transistor with means for providing a non-silicon-based emitter A transistor includes a means for providing a non-silicon-based emitter with a flexible structure to relieve lattice mis-match between the emitter and the base. ... | 06/07/2005 |
| 6903434 | Method and apparatus for integrating flash EPROM and SRAM cells on a common substrate A system for and a method of integrating SRAM cells and flash EPROM cells onto a single silicon substrate includes an area on the silicon substrate where a local oxidation of silicon (LOCOS) isolation technique is implemented and another area on the same silicon sub... | 06/07/2005 |
| 6897095 | Semiconductor process and integrated circuit having dual metal oxide gate dielectric with single metal gate electrode A semiconductor fabrication process includes forming first and second transistors over first and second well regions, respectively where the first transistor has a first gate dielectric and the second transistor has a second gate dielectric different from the first ... | 05/24/2005 |
| 6894361 | Semiconductor device A semiconductor device includes an isolation region which is formed in a semiconductor layer, and a resistance conductive layer which is in a sidewall shape. According to this semiconductor device, the resistance conductive layer having a high resistance can be obta... | 05/17/2005 |
