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| Number | Title | Issue Date |
| 8183664 | Electrostatic discharge protection device, method of manufacturing the same, method of testing the same An electrostatic discharge protection device, a method of manufacturing the same, and a method of testing the same. The electrostatic protection device includes a plurality of device isolation regions formed in a semiconductor substrate at a predetermined width and ... | 05/22/2012 |
| 8154102 | Semiconductor device and manufacturing method thereof A semiconductor device includes groove-like regions that are formed between two adjacent bit lines among a plurality of bit lines each having upper and side surfaces covered with a cap insulating film and a side-wall insulating film, respectively, a SiON film that c... | 04/10/2012 |
| 8138571 | Semiconductor device comprising isolation trenches inducing different types of strain By forming isolation trenches of different types of intrinsic stress on the basis of separate process sequences, the strain characteristics of adjacent active semiconductor regions may be adjusted so as to obtain overall device performance. For example, highly stres... | 03/20/2012 |
| 8120140 | Isolation structure and formation method thereof An isolation structure comprising a substrate is provided. A trench is in the substrate. A sidewall of the trench has a first inclined surface and a second inclined surface. The first inclined surface is located on the second inclined surface. The slope of the first... | 02/21/2012 |
| 8115272 | Silicon dioxide cantilever support and method for silicon etched structures An apparatus includes a semiconductor layer (2) having therein a cavity (4). A dielectric layer (3) is formed on the semiconductor layer. A plurality of etchant openings (24) extend through the dielectric layer for passage of etchant for ... | 02/14/2012 |
| 8106475 | Semiconductor device and method of manufacturing the same A semiconductor device includes a semiconductor substrate formed with a plurality of first element isolation trenches having respective first opening widths and a plurality of second element isolation trenches having larger opening widths than the first opening widt... | 01/31/2012 |
| 8093678 | Semiconductor device and method of fabricating the same A semiconductor device. The device includes an active region isolated by an isolation structure on a substrate, and a dielectric layer overlying the active region and the isolation structure. The dielectric layer comprises a lower part overlying the active region be... | 01/10/2012 |
| 8053861 | Diffusion barrier layers Provided are methods and apparatuses for depositing barrier layers for blocking diffusion of conductive materials from conductive lines into dielectric materials in integrated circuits. The barrier layer may contain copper. In some embodiments, the layers have condu... | 11/08/2011 |
| 8049297 | Semiconductor structure In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a method includes removing a portion of a semiconductor material to form a cavity that extends at least about one micron or greater below t... | 11/01/2011 |
| 8049298 | Isolation trenches for memory devices A first dielectric plug is formed in a portion of a trench that extends into a substrate of a memory device so that an upper surface of the first dielectric plug is recessed below an upper surface of the substrate. The first dielectric plug has a layer of a first di... | 11/01/2011 |
| 8035190 | Semiconductor devices A device comprises a first sub-collector formed in an upper portion of a substrate and a lower portion of a first epitaxial layer and a second sub-collector formed in an upper portion of the first epitaxial layer and a lower portion of a second epitaxial layer. The ... | 10/11/2011 |
| 8030731 | Isolated rectifier diode An isolated diode comprises a floor isolation region, a dielectric-filled trench and a sidewall region extending from a bottom of the trench at least to the floor isolation region. The floor isolation region, dielectric-filled trench and a sidewall region are compri... | 10/04/2011 |
| 8030732 | Semiconductor device and method for manufacturing the same A semiconductor device which has a semiconductor substrate, an isolation insulating film formed in the semiconductor substrate, a conductive pattern formed over the semiconductor substrate and the isolation insulating film, so that a side face of the conductive patt... | 10/04/2011 |
| 8022500 | Semiconductor device having a high aspect ratio isolation trench A semiconductor device having high aspect ratio isolation trenches and a method for manufacturing the same is presented. The semiconductor device includes a semiconductor substrate, a first insulation layer, and a second insulation layer. The semiconductor substrate... | 09/20/2011 |
| 7989912 | Semiconductor device having a compressed device isolation structure The semiconductor device includes a lower device isolation structure formed in a semiconductor substrate to define an active region. The lower device isolation structure has a first compressive stress. An upper device isolation structure is disposed over the lower d... | 08/02/2011 |
| 7982282 | High efficiency amplifier with reduced parasitic capacitance A semiconductor amplifier is provided comprising, a substrate and one or more unit amplifying cells (UACs) formed on the substrate, wherein each UAC is laterally surrounded by a first lateral dielectric filled trench (DFT) isolation wall extending at least to the su... | 07/19/2011 |
| 7982283 | Semiconductor device and method for manufacturing the same A semiconductor device and a method for manufacturing the same that reduces a process defect caused by pattern dependency in chemical mechanical polarization (CMP) or etching is excellent. The semiconductor device includes a device pattern formed on or in a substrat... | 07/19/2011 |
| 7956437 | Isolation structures for integrated circuits A variety of isolation structures for semiconductor substrates include a trench formed in the substrate that is filled with a dielectric material or filled with a conductive material and lined with a dielectric layer along the walls of the trench. The trench may be ... | 06/07/2011 |
| 7948052 | Dual-bit memory device having trench isolation material disposed near bit line contact areas A dual-bit memory device is provided which includes trench isolation material disposed near bit line contact areas. For example, in one implementation a semiconductor memory device is provided in which each memory cell can store two bits of information. The memory d... | 05/24/2011 |
| 7928530 | Semiconductor device having an oxide film formed on a semiconductor substrate sidewall of an element region and on a sidewall of a gate electrode A first isolation is formed on a semiconductor substrate, and a first element region is isolated via the first isolation. A first gate insulating film is formed on the first element region, and a first gate electrode is formed on the first gate insulating film. A se... | 04/19/2011 |
| 7880263 | Method and resulting structure DRAM cell with selected inverse narrow width effect A shallow trench isolation structure for integrated circuits. The structure includes a semiconductor substrate and a buffered oxide layer overlying the semiconductor substrate. A pad nitride layer is overlying the buffered oxide layer. An implanted region is formed ... | 02/01/2011 |
| 7838961 | Method of manufacturing semiconductor device A semiconductor device includes a semiconductor substrate having trenches extending thereinto. A trench type insulating film fills the trenches. The trench type insulating film includes a first and second insulating film and is laminated in a portion of the trenches... | 11/23/2010 |
| 7834415 | Semiconductor device with trench isolation structure and method of manufacturing the same A semiconductor device has: a substrate provided with a trench; and a device isolation structure formed in the trench. The device isolation structure has: a silicon oxynitride film formed on a surface of the substrate through an interfacial oxide film; and an embedd... | 11/16/2010 |
| 7821098 | Trench widening without merging A semiconductor structure. The semiconductor structure includes a semiconductor substrate, a trench in the semiconductor substrate. The trench comprises a side wall which includes {100} side wall surfaces and {110} side wall surfaces. The semiconductor... | 10/26/2010 |
| 7816760 | Semiconductor structure including laminated isolation region A semiconductor structure and a related method for fabrication thereof include an isolation region located within an isolation trench within a semiconductor substrate. The isolation region comprises; (1) a lower lying dielectric plug layer recessed within the isolat... | 10/19/2010 |
| 7804151 | Integrated circuit structure, design structure, and method having improved isolation and harmonics Disclosed are embodiments of a semiconductor structure, a design structure for the semiconductor structure and a method of forming the semiconductor structure. The embodiments reduce harmonics and improve isolation between the active semiconductor layer and the subs... | 09/28/2010 |
| 7804152 | Recessed shallow trench isolation In some embodiments, a memory integrated circuit has different shallow trench isolation structures in the memory circuitry of the memory integrated circuit and the control circuitry of the memory integrated circuit. The isolation dielectric fills the trenches of the... | 09/28/2010 |
| 7791162 | Trench isolation structure, semiconductor assembly comprising such a trench isolation, and method for forming such a trench isolation The present invention provides a trench isolation structure, comprising a trench groove (4) in a semiconductor slab (1) with a buried layer (2). The trench groove (4) is lined with first insulating material (5), then filled with a ... | 09/07/2010 |
| 7786547 | Formation of active area using semiconductor growth process without STI integration A semiconductor device can be formed without use of an STI process. An insulating layer is formed over a semiconductor body. Portions of the insulating layer are removed to expose the semiconductor body, e.g., to expose bare silicon. A semiconductor material, e.g., ... | 08/31/2010 |
| 7772673 | Deep trench isolation and method for forming same According to one exemplary embodiment, a semiconductor die including at least one deep trench isolation region for isolating an electronic device (for example, a bipolar device) includes a trench situated in a substrate of the semiconductor die, where the trench has... | 08/10/2010 |
| 7772672 | Semiconductor constructions The invention includes semiconductor constructions having trenched isolation regions. The trenches of the trenched isolation regions can include narrow bottom portions and upper wide portions over the bottom portions. Electrically insulative material can fill the up... | 08/10/2010 |
| 7768095 | Shallow trench isolation process utilizing differential liners A method of manufacturing an integrated circuit (IC) can utilize a shallow trench isolation (STI) technique. The shallow trench isolation technique can be used in an IC process. Separate liners for the trench are used for NMOS and PMOS regions. The liners can induce... | 08/03/2010 |
| 7759763 | Semiconductor device and a method of manufacturing the same A semiconductor device which, in spite of the existence of a dummy active region, eliminates the need for a larger chip area and improves the surface flatness of the semiconductor substrate. In the process of manufacturing it, a thick gate insulating film for a high... | 07/20/2010 |
| 7745904 | Shallow trench isolation structure for semiconductor device A semiconductor device provides a transistor adjacent an isolation trench. The device may be formed by producing isolation trenches in a semiconductor substrate, filling the trenches with a filler material, creating voids near top edges of the trenches and annealing... | 06/29/2010 |
| 7723817 | Semiconductor device and manufacturing method thereof The shape of a tip of an insulating material of an insulating isolation region is provided as being a concave one recessed below the back surface of an n-semiconductor substrate. This reduces the electric field strength at the corner at which the bottom of the n-sem... | 05/25/2010 |
| 7719080 | Semiconductor device with a conduction enhancement layer A semiconductor device includes a drift layer of a first conductivity type having a doping concentration and a conduction layer also of the first conductivity type on the drift layer that has a doping concentration greater than the doping concentration of the drift ... | 05/18/2010 |
| 7709926 | Device structures for active devices fabricated using a semiconductor-on-insulator substrate and design structures for a radiofrequency integrated circuit Device structure for active devices fabricated in a semiconductor-on-insulator (SOI) substrate and design structures for a radiofrequency integrated circuit. The device structure includes a first isolation region in the semiconductor layer that extends from a top su... | 05/04/2010 |
| 7709927 | Shallow trench isolation structures for semiconductor devices including wet etch barriers A semiconductor device includes a sidewall oxide layer covering an inner wall of a trench, a nitride liner on the sidewall oxide layer and a gap-fill insulating layer filling the trench on the nitride liner. A first impurity doped oxide layer is provided at edge reg... | 05/04/2010 |
| 7705417 | Semiconductor device and method of fabricating isolation region A semiconductor device according to an embodiment of the present invention includes: a semiconductor substrate; an isolation region including a liner film formed so as to contact a lower surface and a lower side surface of an inner wall of a trench formed in the sem... | 04/27/2010 |
| 7705416 | Method for forming horizontal buried channels or cavities in wafers of monocrystalline semiconductor material A method of forming buried cavities in a wafer of monocrystalline semiconductor material with at least one cavity formed in a substrate of monocrystalline semiconductor material by timed TMAH etching silicon; covering the cavity with a material inhibiting epitaxial ... | 04/27/2010 |
