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| Number | Title | Issue Date |
| 8154101 | High voltage diode with reduced substrate injection A high voltage diode in which the n-type cathode is surrounded by an uncontacted heavily doped n-type ring to reflect injected holes back into the cathode region for recombination or collection is disclosed. The dopant density in the heavily doped n-type ring is pre... | 04/10/2012 |
| 8125045 | Dielectric isolation type semiconductor device and manufacturing method therefor A dielectric isolation type semiconductor device includes a dielectric isolation type substrate in which a support substrate, an embedded dielectric layer, and a first conductive type semiconductor substrate of a low impurity concentration are laminated one over ano... | 02/28/2012 |
| 8120139 | Void isolated III-nitride device Isolation of III-nitride devices may be performed with a dopant selective etch that provides a smooth profile with little crystal damage in comparison to previously used isolation techniques. The dopant selective etch may be an electro-chemical or photo-electro-chem... | 02/21/2012 |
| 7667288 | Systems and methods for voltage distribution via epitaxial layers Systems and methods for voltage distribution via epitaxial layers. In accordance with a first embodiment of the present invention, an integrated circuit comprises an epitaxial layer of a connectivity type disposed upon a wafer substrate of an opposite connectivity t... | 02/23/2010 |
| 7485943 | Dielectric isolation type semiconductor device and manufacturing method therefor A dielectric isolation type semiconductor device includes a dielectric isolation type substrate in which a support substrate, an embedded dielectric layer, and a first conductive type semiconductor substrate of a low impurity concentration are laminated one over ano... | 02/03/2009 |
| 7439587 | Semiconductor device and method of manufacturing the same An isolation insulating film (5) of partial-trench type is selectively formed in an upper surface of a silicon layer (4). A power supply line (21) is formed above the isolation insulating film (5). Below the power supply line (21),... | 10/21/2008 |
| 7425745 | Semiconductor device and method for manufacturing the same A semiconductor device includes a semiconductor substrate, an isolation film that is provided in one principal surface of the semiconductor substrate, wiring that is arranged on the isolation film, a diffusion layer that is formed inside the semiconductor substrate ... | 09/16/2008 |
| 7420202 | Electronic device including a transistor structure having an active region adjacent to a stressor layer and a process for forming the electronic device An electronic device can include a transistor structure of a first conductivity type, a field isolation region, and a layer of a first stress type overlying the field isolation region. For example, the transistor structure may be a p-channel transistor structure and... | 09/02/2008 |
| 7402885 | LOCOS on SOI and HOT semiconductor device and method for manufacturing One or more local oxidation of silicon (LOCOS) regions may be formed that apply compressive strain to a channel of a field-effect transistor such as a P-type field-effect transistor (PFET) or other circuit element of a semiconductor device. For instance, a pair of L... | 07/22/2008 |
| 7382015 | Semiconductor device including an element isolation portion having a recess A non-volatile semiconductor memory device, which is intended to prevent data destruction by movements of electric charges between floating gates and thereby improve the reliability, includes element isolation/insulation films buried into a silicon substrate to isol... | 06/03/2008 |
| 7355259 | Photodiode array and optical receiver device including the same Disclosed is a photodiode array which includes a plurality of p-i-n photodiodes arrayed on a semi-insulative semiconductor substrate, each photodiode including an n-type semiconductor layer grown on the substrate, an i-type semiconductor layer grown on the n-type se... | 04/08/2008 |
| 7304334 | Silicon carbide bipolar junction transistors having epitaxial base regions and multilayer emitters and methods of fabricating the same Bipolar junction transistors (BJTs) are provided including silicon carbide (SiC) substrates. An epitaxial SiC base region is provided on the SiC substrate. The epitaxial SiC base region has a first conductivity type. An epitaxial SiC emitter region is also provided ... | 12/04/2007 |
| 7291894 | Vertical charge control semiconductor device with low output capacitance In accordance with an embodiment of the present invention, a MOSFET includes at least two insulation-filled trench regions laterally spaced in a first semiconductor region to form a drift region therebetween, and at least one resistive element located along an outer... | 11/06/2007 |
| 7274073 | Integrated circuit with bulk and SOI devices connected with an epitaxial region An integrated circuit having devices fabricated in both SOI regions and bulk regions, wherein the regions are connected by a trench filled with epitaxially deposited material. The filled trench provides a continuous semiconductor surface joining the SOI and bulk reg... | 09/25/2007 |
| 7259055 | Method of forming high-luminescence silicon electroluminescence device A method for forming a high-luminescence Si electroluminescence (EL) phosphor is provided, with an EL device made from the Si phosphor. The method comprises: depositing a silicon-rich oxide (SRO) film, with Si nanocrystals, having a refractive index in the range of ... | 08/21/2007 |
| 7253486 | Field plate transistor with reduced field plate resistance In one example embodiment, a transistor (100) is provided. The transistor (100) comprises a source (10), a gate (30), a drain (20), and a field plate (40) located between the gate (30) and the drain (20). The f... | 08/07/2007 |
| 7247921 | Semiconductor apparatus and method of manufacturing same, and method of detecting defects in semiconductor apparatus A semiconductor apparatus includes a semiconductor substrate having a device region and a periphery region surrounding the device region; a semiconductor device provided in the device region of the semiconductor substrate; a first electrode pad provided on the semic... | 07/24/2007 |
| 7242061 | Semiconductor device The invention provides semiconductor devices having an output circuit in which transistors do not fail to achieve their original capability, and electrostatic breakdown is difficult to occur. A semiconductor device is equipped with a semiconductor substrate, an elem... | 07/10/2007 |
| 7235857 | Power semiconductor device A semiconductor device is provided in which a plurality of MOSFETs including a vertical MOSFET is formed on a substrate. The device includes a silicon carbide substrate having front and back surfaces facing each other, an isolating region formed in the substrate to ... | 06/26/2007 |
| 7224011 | Image sensors and methods of manufacturing the same Image sensors and methods of manufacturing an image sensor are disclosed. A disclosed photo diode may receive short wavelength light in its depletion region without exhibiting defective phenomenon such as noise and dark current. In the illustrated example, this perf... | 05/29/2007 |
| 7221035 | Semiconductor structure avoiding poly stringer formation The present invention discloses a semiconductor structure avoiding the poly stringer formation in semiconductor processing. A semiconductor device is divided into a memory cell area and a peripheral portion. A plurality of parallel first isolation devices are positi... | 05/22/2007 |
| 7193272 | Semiconductor device and method of manufacturing the same An isolation insulating film (5) of partial-trench type is selectively formed in an upper surface of a silicon layer (4). A power supply line (21) is formed above the isolation insulating film (5). Below the power supply line (21),... | 03/20/2007 |
| 7190042 | Self-aligned STI for narrow trenches A self-aligned shallow trench isolation region for a memory cell array is formed by etching a plurality of vertical deep trenches in a substrate and coating the trenches with an oxidation barrier layer. The oxidation barrier layer is recessed in portions of the tren... | 03/13/2007 |
| 7179750 | Method for manufacturing multi-thickness gate dielectric layer of semiconductor device In a method for manufacturing a multi-thickness gate dielectric layer of a semiconductor device, a first dielectric layer is formed on a semiconductor substrate. A second dielectric layer is formed using a different dielectric material from the material constituting... | 02/20/2007 |
| 7176548 | Complementary analog bipolar transistors with trench-constrained isolation diffusion A semiconductor substrate includes a pair of trenches filled with a dielectric material. Dopant introduced into the mesa between the trenches is limited from diffusing laterally when the substrate is subjected to thermal processing. Therefore, semiconductor devices ... | 02/13/2007 |
| 7173316 | Semiconductor device An N type semiconductor layer is epitaxially grown on a P type semiconductor substrate of which one end is grounded, and an element isolation layer made of a P type diffusion layer is formed by means of diffusion around the N type semiconductor layer in order to ele... | 02/06/2007 |
| 7170109 | Heterojunction semiconductor device with element isolation structure A technique enabling to improve element isolation characteristic of a semiconductor device is provided. An element isolation structure is provided in a semiconductor substrate in which a silicon layer, a compound semiconductor layer and a semiconductor layer are lam... | 01/30/2007 |
| 7161223 | Integrated circuit with a PN junction diode Apparatus and Methods for the self-alignment of separated regions in a lateral MOSFET of an integrate circuit. In one embodiment, a method comprising, forming a relatively thin dielectric layer on a surface of a substrate. Forming a first region of relatively thick ... | 01/09/2007 |
| 7146596 | Integrated circuit chip having a ringed wiring layer interposed between a contact layer and a wiring grid An integrated circuit chip having a contact layer that includes a plurality of Vdd, Vddx, ground and I/O contacts arranged in a generally radial pattern having diagonal and major axis symmetry and generally defining four quadrants. A multilayer X-Y power grid is loc... | 12/05/2006 |
| 7145187 | Substrate independent multiple input bi-directional ESD protection structure In a multiple input ESD protection structure, the inputs are isolated from the substrate by highly doped regions of opposite polarity to the input regions. Dual polarity is achieved by providing a symmetrical structure with n+ and p+ regions forming each dual polari... | 12/05/2006 |
| 7141833 | Photodiode Apart from a semiconductor substrate and a photosensitive region in the semiconductor substrate, which comprises a space charge zone region for generating a diffusion current portion and a diffusion region for generating a diffusion current portion, a photodiode inc... | 11/28/2006 |
| 7135755 | Integrated semiconductor device providing for preventing the action of parasitic transistors An electric motor drive system is disclosed which includes a required number of motor driver circuits connected one to each motor armature coil. Fabricated in the form of an integrated circuit, each such motor driver circuit has a parasitic transistor unavoidably cr... | 11/14/2006 |
| 7122388 | Method of detecting misalignment of ion implantation area A method of detecting misalignment of ion implantation areas comprises forming at least one standard pattern consisting of a first area and a second area for use in measuring resistance, implanting first and second conduction type impurity ions into the first and se... | 10/17/2006 |
| 7071496 | Electronic device and method for manufacturing the same An electronic device including a new oxide layer and a method for manufacturing the same are provided. The electronic device of the present invention includes an oxide layer, which is formed of an oxide containing an element from group IIa, an element from group IIb... | 07/04/2006 |
| 7071527 | Semiconductor element and manufacturing method thereof A p-channel MOSFET (1) includes a semiconductor substrate (2), an epitaxial region (3), a second diffusion region (6), and a drain region. The epitaxial region (3) is formed on the upper surface of the semiconductor substrate (2... | 07/04/2006 |
| 7049185 | Semiconductor device having dummy gates and its manufacturing method In a semiconductor device including active areas where transistors are formed and a field area for isolating the active areas from each other, the field area has a plurality of dummy areas where dummy gates are formed. ... | 05/23/2006 |
| 7042096 | Single semiconductor element in a flip chip construction A substrate layer is provided at the rear side of a single semiconductor element. An active layer is arranged between the substrate layer and a contact side of the single semiconductor element. At least two solder contacts are electrically connected to the active la... | 05/09/2006 |
| 7038292 | Substrate isolation design A substrate isolation design includes a P substrate, a P well positioned on the P substrate, at least a device positioned in the P well, and at least a P substrate guard ring surrounding the device. A P+ guard ring, an N well guard ring, or a deep N well guard ring ... | 05/02/2006 |
| 7038290 | Integrated circuit device An integrated circuit device comprising: a body of a first solid material having an upper surface and a major bottom surface; a pocket of a second solid material having a top surface and a side surface, and a botto... | 05/02/2006 |
| 7030455 | Integrated electromagnetic shielding device To isolate at least one electric or electronic element (16, 58), for example an interconnection integrated onto a semiconductor substrate (12), this device comprises at least one isolation means chosen from an isolating layer (84, 86, 90) extend... | 04/18/2006 |
