Bizarre Patents
Combination Beverage Container and Spittoon
A combination beverage container and spittoon includes a bottom portion including outer wall and a first inner wall defining a spittoon space.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 7423324 | Double-gate MOS transistor, double-gate CMOS transistor, and method for manufacturing the same In a double-gate MOS transistor, a substrate, an insulating layer, and a semiconductor layer are formed or laminated in that order, an opening extending to the insulating layer is formed in the semiconductor layer while leaving an island-shaped region, the island-sh... | 09/09/2008 |
| 7420258 | Semiconductor device having trench structures and method In one embodiment, a pair of sidewall passivated trench contacts is formed in a substrate to provide electrical contact to a sub-surface feature. A doped region is diffused between the pair of sidewall passivated trenches to provide low resistance contacts. ... | 09/02/2008 |
| 7420202 | Electronic device including a transistor structure having an active region adjacent to a stressor layer and a process for forming the electronic device An electronic device can include a transistor structure of a first conductivity type, a field isolation region, and a layer of a first stress type overlying the field isolation region. For example, the transistor structure may be a p-channel transistor structure and... | 09/02/2008 |
| 7382015 | Semiconductor device including an element isolation portion having a recess A non-volatile semiconductor memory device, which is intended to prevent data destruction by movements of electric charges between floating gates and thereby improve the reliability, includes element isolation/insulation films buried into a silicon substrate to isol... | 06/03/2008 |
| 7361944 | Electrical device with a plurality of thin-film device layers A highly reliable electrical device having a multilayered structure of a plurality of thin-film device layers and a method for manufacturing the same are provided. An electrical device includes a plurality of thin-film layers deposited and including a plurality of t... | 04/22/2008 |
| 7358588 | Trench isolation type semiconductor device which prevents a recess from being formed in a field region A trench isolation type semiconductor device in which a recess is prevented from being formed in a field region and a method of fabricating the same are provided. The trench isolation type semiconductor device includes a semiconductor substrate defined by an active ... | 04/15/2008 |
| 7338885 | Alignment mark and method for manufacturing a semiconductor device having the same In a method for manufacturing a semiconductor device having an alignment mark, a buffer layer is formed on a substrate. A trench is formed at an isolation region of the substrate. The trench is filled with an insulating layer. An alignment groove is formed on the in... | 03/04/2008 |
| 7327008 | Structure and method for mixed-substrate SIMOX technology The present invention provides a semiconductor structure that includes a substrate having a crystal lattice; a first structure formed in a first region of the substrate, the first structure includes at least a heterostructure that generates a lattice stress in said ... | 02/05/2008 |
| 7315064 | Bonded wafer and method of producing bonded wafer The present invention provides a bonded wafer, wherein at least a silicon single crystal layer is formed on a silicon single crystal wafer, the silicon single crystal layer has a crystal plane orientation of {110}, and the silicon single crystal wafer has a crystal ... | 01/01/2008 |
| 7294901 | Semiconductor device with improved resurf features including trench isolation structure A p impurity region (3) defines a RESURF isolation region in an n− semiconductor layer (2). A trench isolation structure (8a) and the p impurity region (3) together define a trench isolation region in the n− | 11/13/2007 |
| 7291894 | Vertical charge control semiconductor device with low output capacitance In accordance with an embodiment of the present invention, a MOSFET includes at least two insulation-filled trench regions laterally spaced in a first semiconductor region to form a drift region therebetween, and at least one resistive element located along an outer... | 11/06/2007 |
| 7285825 | Element formation substrate for forming semiconductor device A support-side substrate having a thermal oxide film on the major surface is bonded to an active-layer-side substrate having a thermal oxide film on the major surface while making the major surfaces oppose each other. The active-layer-side substrate and part of the ... | 10/23/2007 |
| 7279751 | Semiconductor laser device and manufacturing method thereof It is an object of the present invention to provide a semiconductor laser device with high-yielding in which a clack generated in an epitaxial growth layer is restrained and to the manufacturing method thereof, the semiconductor laser device includes a GaN substrate... | 10/09/2007 |
| 7259428 | Semiconductor device using SOI structure having a triple-well region A semiconductor device includes a support substrate, a buried insulation film, provided on the support substrate, having a thickness of 5 to 10 nm, a silicon layer provided on the buried insulation film, a MOSFET provided in the silicon layer, and a triple-well regi... | 08/21/2007 |
| 7253082 | Pasted SOI substrate, process for producing the same and semiconductor device A plurality of recessed portions having different depths is formed in a surface of the active layer wafer or in a bonding surface of the supporting substrate wafer. Those wafers are bonded to each other with an insulation film interposed therebetween. This allows a ... | 08/07/2007 |
| 7247908 | Method of fabricating a FinFET A FinFET structure and method of forming a FinFET device. The method includes: (a) providing a semiconductor substrate, (b) forming a dielectric layer on a top surface of the substrate; (c) forming a silicon fin on a top surface of the dielectric layer; (d) forming ... | 07/24/2007 |
| 7244990 | Semiconductor device On an SOI substrate, a hydrogen ion implantation section in which distribution of hydrogen ions peaks in a BOX layer (buried oxide film layer), and a single-crystal silicon thin-film transistor are formed. Then this SOI substrate is bonded with an insulating substra... | 07/17/2007 |
| 7207025 | Sea-of-cells array of transistors The invention concerns integrated circuits in which a MACRO is embedded in a standard cell array. One level of metal is devoted exclusively to non-local interconnect, and a layer of polysilicon is devoted to local interconnect, thereby saving significant space. ... | 04/17/2007 |
| 7202518 | Integrated dynamic random access memory element, array and process for fabricating such elements An integrated dynamic random access memory element includes two cells for the storage of two respective bits. A source region and a drain region are included. Each cell comprises a field-effect transistor having a gate and an intermediate portion which extend betwee... | 04/10/2007 |
| 7183585 | Semiconductor device and a method for the manufacture thereof To provide a semiconductor device that excels in the manufacturing efficiency and device reliability, and a method for the manufacture thereof. The side of a device is composed of scribed grooves 13 and a cleavage plane 100. ... | 02/27/2007 |
| 7180109 | Field effect transistor and method of fabrication The present invention is a novel field effect transistor having a channel region formed from a narrow bandgap semiconductor film formed on an insulating substrate. A gate dielectric layer is formed on the narrow bandgap semiconductor film. A gate electrode is then f... | 02/20/2007 |
| 7170109 | Heterojunction semiconductor device with element isolation structure A technique enabling to improve element isolation characteristic of a semiconductor device is provided. An element isolation structure is provided in a semiconductor substrate in which a silicon layer, a compound semiconductor layer and a semiconductor layer are lam... | 01/30/2007 |
| 7166894 | Schottky power diode with SiCOI substrate and process for making such diode The present invention relates to a power junction device including a substrate of the SiCOI type with a layer of silicon carbide (16) insulated from a solid carrier (12) by a buried layer of insulant (14), and including at least one Schottky con... | 01/23/2007 |
| 7163640 | Methods and systems for laser processing The described embodiments relate to slotted substrates. One exemplary method forms a feature into a substrate, at least in part, by directing a laser beam at the substrate. During at least a portion of said directing, the method supplies a conductive material proxim... | 01/16/2007 |
| 7148543 | Semiconductor chip which combines bulk and SOI regions and separates same with plural isolation regions A semiconductor chip includes a base substrate, a bulk device region having a bulk growth layer on a part of the base substrate, an SOI device region having a buried insulator on the base substrate and a silicon layer on the buried insulator, and a boundary layer lo... | 12/12/2006 |
| 7148558 | Versatile system for limiting mobile charge ingress in SOI semiconductor structures Disclosed are apparatus and method for limiting mobile charge (314) ingress within a silicon-on-insulator (SOI) substrate (300). A mask (308) is applied to the substrate to form an aperture (210) over a desired portion of the substrate ne... | 12/12/2006 |
| 7122865 | SOI wafer and process for producing it An SOI wafer, includes a substrate made from silicon, an electrically insulating layer with a thermal conductivity of at least 1.6 W/(Km) and a single-crystal silicon layer with a thickness of from 10 nm to 10 μm, a standard deviation of at most 5% from the mean la... | 10/17/2006 |
| 7109551 | Semiconductor device A semiconductor structure with device trench and a semiconductor device in the device trench, that enables realization of high integration, lowered on-resistance, reduction in switching losses and a high operation speed in a semiconductor device provided with a late... | 09/19/2006 |
| 7098473 | Thin film transistor, and organic EL display thereof Thin film transistor, and organic EL display of the same and method for fabricating the same, including a high temperature substrate of metal or ceramic, a semiconductor layer formed in a region of the substrate having a source region and a drain region, a source el... | 08/29/2006 |
| 7084451 | Circuits with a trench capacitor having micro-roughened semiconductor surfaces A method for forming a trench capacitor. The method includes forming a trench in a semiconductor substrate. A conformal layer of semiconductor material is deposited in the trench. The surface of the conformal layer of semiconductor material is roughened. An insulato... | 08/01/2006 |
| 7084496 | Method and apparatus for providing optoelectronic communication with an electronic device An optoelectronic assembly for an electronic system includes a transparent substrate having a first surface and an opposite second surface, the transparent substrate being thermally conductive and being metallized on the surface. A support electronic chip set is con... | 08/01/2006 |
| 7075151 | Semiconductor memory device for storing data as state of majority carriers accumulated in channel body and method of manufacturing the same A semiconductor memory device comprises a substrate; a first semiconductor layer of a first conduction type having a single crystalline structure isolated from the substrate by an insulator layer; a plurality of memory transistors, each having a gate electrode conne... | 07/11/2006 |
| 7075150 | Ultra-thin Si channel MOSFET using a self-aligned oxygen implant and damascene technique The present invention provides a thin channel MOSFET having low external resistance. In broad terms, a silicon-on-insulator structure comprising a SOI layer located atop a buried insulating layer, said SOI layer having a channel region which is thinned by the presen... | 07/11/2006 |
| 7057223 | Circuit and method for a folded bit line memory cell with vertical transistor and trench capacitor A memory cell for a memory array in a folded bit line configuration. The memory cell includes an access transistor formed in a pillar of single crystal semiconductor material. The access transistor has first and second source/drain regions and a body region that are... | 06/06/2006 |
| 7049196 | Vertical gain cell and array for a dynamic random access memory and method for forming the same A vertical gain memory cell including an n-channel metal-oxide semiconductor field-effect transistor (MOSFET) and p-channel junction field-effect transistor (JFET) transistors formed in a vertical pillar of semiconductor material is provided. The body portion of the... | 05/23/2006 |
| 7034362 | Double silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) structures A SOI MOSFET structure having a reduced step height between the various semiconductor layers without adversely affecting the junction capacitance of the semiconductor device formed on the uppermost semiconductor layer as well as a method of fabricating the same are ... | 04/25/2006 |
| 7023051 | Localized strained semiconductor on insulator One aspect of this disclosure relates to a method for straining a transistor body region. In various embodiments, oxygen ions are implanted to a predetermined depth in a localized region of a semiconductor substrate, and the substrate is annealed. Oxide growth withi... | 04/04/2006 |
| 6995427 | Semiconductor structure for providing strained crystalline layer on insulator and method for fabricating same A semiconductor structure having a high-strained crystalline layer with a low crystal defect density and a method for fabricating such a semiconductor structure are disclosed. The structure includes a substrate having a first material comprising germanium or a Group... | 02/07/2006 |
| 6995447 | Silicon on insulator device having trench isolation layer and method for manufacturing the same A silicon-on-insulator (SOI) device and a method for manufacturing the same includes a substrate, which includes a base layer, a buried oxide layer, and a semiconductor layer, and an isolation layer which is formed in a trench that defines an active region on the se... | 02/07/2006 |
| 6967351 | Finfet SRAM cell using low mobility plane for cell stability and method for forming The present invention provides a device design and method for forming the same that results in Fin Field Effect Transistors having different gains without negatively impacting device density. The present invention forms relatively low gain FinFET transistors in a lo... | 11/22/2005 |
